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? 2002-2015 microchip technology inc. ds30009605g-page 1 low-power features power managed modes: - run: cpu on, peripherals on - idle: cpu off, peripherals on - sleep: cpu off, peripherals off power consumption modes: - pri_run: 150 ? a, 1 mhz, 2v - pri_idle: 37 ? a, 1 mhz, 2v - sec_run: 14 ? a, 32 khz, 2v - sec_idle: 5.8 ? a, 32 khz, 2v - rc_run: 110 ? a, 1 mhz, 2v - rc_idle: 52 ? a, 1 mhz, 2v - sleep: 0.1 ? a, 1 mhz, 2v timer1 oscillator: 1.1 ? a, 32 khz, 2v watchdog timer: 2.1 ? a two-speed oscillator start-up oscillators four crystal modes: - lp, xt, hs: up to 25 mhz - hspll: 4-10 mhz (16-40 mhz internal) two external rc modes, up to 4 mhz two external clock modes, up to 40 mhz internal oscillator block: - 8 user-selectable frequencies: 31 khz, 125 khz, 250 khz, 500 khz, 1 mhz, 2 mhz, 4 mhz, 8 mhz - 125 khz to 8 mhz calibrated to 1% - two modes select one or two i/o pins - osctune C allows user to shift frequency secondary oscillator using timer1 @ 32 khz fail-safe clock monitor - allows for safe shutdown if peripheral clock stops peripheral highlights high current sink/source 25 ma/25 ma three external interrupts enhanced capture/compare/pwm (eccp) module: - one, two or four pwm outputs - selectable polarity - programmable dead time - auto-shutdown and auto-restart - capture is 16-bit, max resolution 6.25 ns (t cy /16) - compare is 16-bit, max resolution 100 ns (t cy ) compatible 10-bit, up to 13-channel analog-to- digital converter module (a/d) with programmable acquisition time enhanced usart module: - supports rs-485, rs-232 and lin 1.2 - auto-wake-up on start bit - auto-baud detect special microcontroller features 100,000 erase/write cycle enhanced flash program memory, typical 1,000,000 erase/write cycle data eeprom memory, typical flash/data eeprom retention: > 40 years self-programmable under software control priority levels for interrupts 8 x 8 single-cycle hardware multiplier extended watchdog timer (wdt): - programmable period from 41 ms to 131s - 2% stability over v dd and temperature single-supply 5v in-circu it serial programming? (icsp?) via two pins in-circuit debug (icd) via two pins wide operating voltage range: 2.0v to 5.5v device program memory data memory i/o 10-bit a/d (ch) eccp (pwm) eusart timers 8/16-bit flash (bytes) # single-word instructions sram (bytes) eeprom (bytes) pic18f1220 4k 2048 256 256 16 7 1 y 1/3 pic18f1320 8k 4096 256 256 16 7 1 y 1/3 18/20/28-pin high-per formance, enhanced flash mcus with 10-bit a/d pic18f1220/1320 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 2 ? 2002-2015 microchip technology inc. pin diagrams rb3/ccp1/p1a rb2/p1b/int2 osc1/clki/ra7 osc2/clko/ra6 v dd /av dd rb7/pgd/t1osi/ rb6/pgc/t1oso/ rb5/pgm/kbi1 rb4/an6/rx/ ra0/an0 ra1/an1/lvdin ra4/t0cki mclr /v pp /ra5 v ss /av ss ra2/an2/v ref - ra3/an3/v ref + rb0/an4/int0 rb1/an5/tx/ 12 3 4 5 6 7 8 9 1817 16 15 14 13 12 11 10 pic18f1x20 18-pin pdip, soic rb3/ccp1/p1a rb2/p1b/int2 osc1/clki/ra7 osc2/clko/ra6 v dd rb7/pgd/t1osi/ rb6/pgc/t1oso/ rb5/pgm/kbi1 rb4/an6/rx/ ra0/an0 ra1/an1/lvdin ra4/t0cki mclr /v pp /ra5 v ss ra2/an2/v ref - ra3/an3/v ref + rb0/an4/int0 rb1/an5/tx/ 12 3 4 5 7 8 9 10 2019 18 17 16 14 13 12 11 pic18f1x20 av dd av ss 61 5 20-pin ssop 28-pin qfn 16 2 ra0/an0 nc ra4/t0cki mclr /v pp /ra5 nc av ss nc ra2/an2/v ref - ra3/an3/v ref + ra1/an1/lvdin osc1/clki/ra7 osc2/clko/ra6 v dd ncav dd rb7/pgd/t1osi/p1d/kbi3 rb6/pgc/t1oso/t13cki/p1c/kbi2 nc rb5/pgm/kbi1 7 pic18f1x20 1 3 6 5 4 15 21 19 20 17 18 22 28 26 27 23 24 25 14 8 10 9 13 12 11 v ss nc nc rb2/p1b/int2 rb0/an4/int0 rb1/an5/tx/ck/int1 nc rb4/an6/rx/dt/kbi0 rb3/ccp1/p1a t13cki/p1c/kbi2 p1d/kbi3 ck/int1 dt/kbi0 p1d/kbi3 t13cki/p1c/kbi2 ck/int1 dt/kbi0 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 3 pic18f1220/1320 table of contents 1.0 device overview ....................................................... ...................................................... ............................................................. 5 2.0 oscillator configurations ..................................... .............................................................. ......................................................... 10 3.0 power managed modes ............................................ ................................................... .......... .................................................... 18 4.0 reset .......................................................................................... ................................................................................................ 31 5.0 memory organization .......................................... ................................................... ............ ........................................................ 39 6.0 flash program memory.................................................................. ...................................... ...................................................... 55 7.0 data eeprom memory ..................................................................... ..................................... ................................................... 64 8.0 8 x 8 hardware multiplier...................................................... ............................................. ......................................................... 68 9.0 interrupts .................................................................................... ................................................................................................ 70 10.0 i/o ports ....................................................................................... ........................... ................................................................... 83 11.0 timer0 module .............................................. ................................................... ............. ............................................................. 95 12.0 timer1 module .............................................. ................................................... ............. ............................................................. 98 13.0 timer2 module .............................................. ................................................... ............. ........................................................... 104 14.0 timer3 module .............................................. ................................................... ............. ........................................................... 106 15.0 enhanced capture/compare/pwm (eccp) module.................................... ............................................. ............................... 109 16.0 enhanced addressable universal synchronous asynchronous receiver transmitter (eusart) ..................................... . .... 126 17.0 10-bit analog-to-digital converter (a/d) module ................................ ............................................ ......................................... 149 18.0 low-voltage detect .......................................... ................................................... ............ ......................................................... 160 19.0 special features of the cpu...................................................... .......................................... .................................................... 165 20.0 instruction set summary ........................................................ ............................................ ...................................................... 184 21.0 development support............................................ ................................................... ......... ....................................................... 226 22.0 electrical characteristics ........................................................ ......................................... ......................................................... 230 23.0 dc and ac characteristics graphs and tables................................... ............................................. ....................................... 262 24.0 packaging information..................................................... ................................................. ........................................................ 280 appendix a: revision history.......................................... ................................................... ...... .......................................................... 290 appendix b: device differences ........................................... ................................................... ... ....................................................... 290 appendix c: conversion considerations ............................................. ............................................. ................................................. 291 appendix d: migration from baseline to enhanced devices................................. ....................................... ...................................... 291 appendix e: migration from mid-range to enhanced devices .................................. ..................................... ................................... 292 appendix f: migration from high-end to enhanced devices ................................... ..................................... ..................................... 292 the microchip web site ....................................................................... .................................. ............................................................ 293 customer change notification service ....................................... ................................................... . ................................................... 293 customer support............................................... ................................................... ............. ............................................................... 293 pic18f1220/1320 product identification system .................................... .............................................. ............................................ 294 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 4 ? 2002-2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versio n number, (e.g., ds30000000a is ve rsion a of document ds30000000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 5 pic18f1220/1320 1.0 device overview this document contains device specific information for the following devices: this family offers the advantages of all pic18 microcon- trollers C namely, high computational performance at an economical price C with the addition of high endurance enhanced flash program memory. on top of these fea- tures, the pic18f1220/1320 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 new core features 1.1.1 power modes all of the devices in the pic18f1220/1320 family incor- porate a range of features that can significantly reduce power consumption during operation. key items include: alternate run modes: by clocking the controller from the timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. multiple idle modes: the controller can also run with its cpu core disabled, but the peripherals are still active. in these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. on-the-fly mode switching: the power managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their applications software design. lower consumption in key modules: the power requirements for both timer1 and the watchdog timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 ? a, respectively. 1.1.2 multiple oscillator options and features all of the devices in the pic18f1220/1320 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. these include: four crystal modes, using crystals or ceramic resonators. two external clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output), or one pin (oscillator input, with the second pin reassigned as general i/o). two external rc oscillator modes, with the same pin options as the external clock modes. an internal oscillator block, which provides an 8 mhz clock (2% accuracy) and an intrc source (approximately 31 khz, stable over temperature and v dd ), as well as a range of six user-selectable clock frequencies (from 125 khz to 4 mhz) for a total of 8 clock frequencies. besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock fail- ure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation, or a safe application shutdown. two-speed start-up: this option allows the internal oscillator to serve as the clock source from power- on reset, or wake-up from sleep mode, until the primary clock source is available. this allows for code execution during what would otherwise be the clock start-up interval and can even allow an appli- cation to perform routine background activities and return to sleep without returning to full-power operation. 1.2 other special features memory endurance: the enhanced flash cells for both program memory and data eeprom are rated to last for many thousands of erase/write cycles C up to 100,000 for program memory and 1,000,000 for eeprom. data retention without refresh is conservatively estimated to be greater than 40 years. self-programmability: these devices can write to their own program memory spaces under internal software control. by using a bootloader routine located in the protected boot block at the top of pro- gram memory, it becomes possible to create an application that can update itself in the field. enhanced ccp module: in pwm mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. other features include auto-shutdown, for disabling pwm outputs on interrupt or other select conditions and auto-restart, to reactivate outputs once the condition has cleared. enhanced usart: this serial communication module features automatic wake-up on start bit and automatic baud rate detection and supports rs-232, rs-485 and lin 1.2 protocols, making it ideally suited for use in local interconnect network (lin) bus applications. 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over two minutes that is stable across operating voltage and temperature. pic18f1220 pic18f1320 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 6 ? 2002-2015 microchip technology inc. 1.3 details on individual family members devices in the pic18f1220/1320 family are available in 18-pin, 20-pin and 28-pin packages. a block diagram for this device family is shown in figure 1-1 . the devices are differentiated from each other only in the amount of on-chip flash program memory (4 kbytes for the pic18f1220 device, 8 kbytes for the pic18f1320 device). these and other features are summarized in ta b l e 1 - 1 . a block diagram of the pic18f1220/1320 device architecture is provided in figure 1-1 . the pinouts for this device family are listed in ta b l e 1 - 2 . table 1-1: device features features pic18f1220 pic18f1320 operating frequency dc C 40 mhz dc C 40 mhz program memory (bytes) 4096 8192 program memory (instructions) 2048 4096 data memory (bytes) 256 256 data eeprom memory (bytes) 256 256 interrupt sources 15 15 i/o ports ports a, b ports a, b timers 4 4 enhanced capture/compare/pwm modules 1 1 serial communications enhanced usart enhanced usart 10-bit analog-to-digital module 7 input channels 7 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable low-voltage detect yes yes programmable brown-out reset yes yes instruction set 75 instructions 75 instructions packages 18-pin sdip 18-pin soic 20-pin ssop 28-pin qfn 18-pin sdip 18-pin soic 20-pin ssop 28-pin qfn downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 7 pic18f1220/1320 figure 1-1: pic18f1220/1320 block diagram instruction decode & control porta portb ra4/t0cki mclr /v pp /ra5 (1) enhanced timer0 timer1 timer2 ra3/an3/v ref + ra2/an2/v ref - ra1/an1/lvdin ra0/an0 data latch data ram address latch address<12> 12 (2) bsr fsr0 fsr1 fsr2 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bit op 8 8 alu<8> 8 address latch (8 kbytes) data latch 20 21 21 16 8 8 8 inc/dec logic 21 8 data bus<8> 8 instruction 12 3 rom latch timer3 bank0, f pclatu pcu osc2/clko/ra6 (2) usart 8 register table latch ta b l e p o i n t e r < 2 > inc/dec logic rb0/an4/int0 rb4/an6/rx/dt/kbi0 rb1/an5/tx/ck/int1 rb2/p1b/int2 rb3/ccp1/p1a rb5/pgm/kbi1 rb6/pgc/t1oso/ rb7/pgd/t1osi/ osc2/clki/ra7 (2) decode power-up timer power-on reset watchdog timer v dd , v ss brown-out reset precision reference voltage low-voltage programming in-circuit debugger oscillator start-up timer timing generation osc1 (2) osc2 (2) t1osi t1oso intrc oscillator fail-safe clock monitor note 1: ra5 is available only when the mclr reset is disabled. 2: osc1, osc2, clki and clko are only available in select oscillator modes and when these pins a re not being used as digital i/o. refer to section 2.0 ?oscillator configurations? for additional information. 8 ccp enhanced t13cki/p1c/kbi2 program memory (4 kbytes) pic18f1220 pic18f1320 a/d converter data eeprom p1d/kbi3 mclr (1) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 8 ? 2002-2015 microchip technology inc. table 1-2: pic18f1220/1320 pinout i/o descriptions pin name pin number pin type buffer type description pdip/ soic ssop qfn mclr /v pp /ra5 mclr v pp ra5 441 i p i st st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki/ra7 osc1 clki ra7 16 18 21 ii i/o st cmos st oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 15 17 20 oo i/o st oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc, ec and intrc modes, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes instruction cycle rate. general purpose i/o pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 112 6 i/o i st analog digital i/o. analog input 0. ra1/an1/lvdin ra1 an1 lvdin 222 7 i/o ii st analog analog digital i/o. analog input 1. low-voltage detect input. ra2/an2/v ref - ra2 an2 v ref - 677 i/o ii st analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 788 i/o ii st analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 332 8 i/o i st/od st digital i/o. open-drain when configured as output. timer0 external clock input. ra5 see the mclr /v pp /ra5 pin. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no p diode to v dd ) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 9 pic18f1220/1320 portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/an4/int0 rb0 an4 int0 899 i/o ii ttl analog st digital i/o. analog input 4. external interrupt 0. rb1/an5/tx/ck/int1 rb1 an5 tx ck int1 91 01 0 i/o i o i/o i ttl analog stst digital i/o. analog input 5. eusart asynchronous transmit. eusart synchronous clock (see related rx/dt). external interrupt 1. rb2/p1b/int2 rb2 p1b int2 17 19 23 i/o o i ttl st digital i/o. enhanced ccp1/pwm output. external interrupt 2. rb3/ccp1/p1a rb3 ccp1 p1a 18 20 24 i/o i/o o ttl st digital i/o. capture 1 input/compare 1 output/pwm 1 output. enhanced ccp1/pwm output. rb4/an6/rx/dt/kbi0 rb4an6 rx dt kbi0 10 11 12 i/o ii i/o i ttl analog stst ttl digital i/o. analog input 6. eusart asynchronous receive. eusart synchronous data (see related tx/ck). interrupt-on-change pin. rb5/pgm/kbi1 rb5 pgm kbi1 11 12 13 i/o i/o i ttl st ttl digital i/o. low-voltage icsp? programming enable pin. interrupt-on-change pin. rb6/pgc/t1oso/ t13cki/p1c/kbi2 rb6 pgc t1oso t13cki p1c kbi2 12 13 15 i/o i/o o i o i ttl st st ttl digital i/o. in-circuit debugger and icsp programming clock pin. timer1 oscillator output. timer1/timer3 external clock output. enhanced ccp1/pwm output. interrupt-on-change pin. rb7/pgd/t1osi/ p1d/kbi3 rb7 pgd t1osi p1d kbi3 13 14 16 i/o i/o i o i ttl st cmos ttl digital i/o. in-circuit debugger and icsp programming data pin. timer1 oscillator input. enhanced ccp1/pwm output. interrupt-on-change pin. v ss 5 5, 6 3, 5 p ground reference for logic and i/o pins. v dd 14 15, 16 17, 19 p positive supply for logic and i/o pins. nc 18 no connect. table 1-2: pic18f1220/1320 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip/ soic ssop qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no p diode to v dd ) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 10 ? 2002-2015 microchip technology inc. 2.0 oscillator configurations 2.1 oscillator types the pic18f1220 and pic18f1320 devices can be operated in ten different oscillator modes. the user can program the configuration bits, fosc3:fosc0, in configuration register 1h to select one of these ten modes: 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. hspll high-speed crystal/resonator with pll enabled 5. rc external resistor/capacitor with f osc /4 output on ra6 6. rcio external resistor/capacitor with i/o on ra6 7. intio1 internal oscillator with f osc /4 output on ra6 and i/o on ra7 8. intio2 internal oscillator with i/o on ra6 and ra7 9. ec external clock with f osc /4 output 10. ecio external clock with i/o on ra6 2.2 crystal oscillator/ceramic resonators in xt, lp, hs or hspll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. the oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (xt, lp, hs or hspll configuration) table 2-1: capacitor selection for ceramic resonators note: use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. typical capacitor values used: mode freq. osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 56 pf 47 pf 33 pf 56 pf 47 pf 33 pf hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. these capacitors were tested with the resonators listed below for basic start-up and operation. these values are not optimized . different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following tab l e 2 - 2 for additional information. resonators used: 455 khz 4.0 mhz 2.0 mhz 8.0 mhz 16.0 mhz note 1: see ta b l e 2 - 1 and table 2-2 for initial values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the oscillator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18fxxxx r s (2) internal downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 11 pic18f1220/1320 table 2-2: capacitor selection for crystal oscillator an external clock source may also be connected to the osc1 pin in the hs mode, as shown in figure 2-2 . figure 2-2: external clock input operation (hs osc configuration) 2.3 hspll a phase locked loop (pll) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. this may be useful for customers who are concerned with emi due to high-frequency crystals. the hspll mode makes use of the hs mode oscillator for frequencies up to 10 mhz. a pll then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 mhz. the pll is enabled only when the oscillator configura- tion bits are programmed for hspll mode. if programmed for any other mode, the pll is not enabled. figure 2-3: pll block diagram osc type crystal freq. typical capacitor values tested: c1 c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 1 mhz 33 pf 33 pf 4 mhz 27 pf 27 pf hs 4 mhz 27 pf 27 pf 8 mhz 22 pf 22 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values are not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. crystals used: 32 khz 4 mhz 200 khz 8 mhz 1 mhz 20 mhz note 1: higher capacitance increases the stability of oscillator, but also increases the start- up time. 2: when operating below 3v v dd , or when using certain ceramic resonators at any voltage, it may be necessary to use the hs mode or switch to a crystal oscillator. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: r s may be required to avoid overdriving crystals with low drive level specification. 5: always verify oscillator performance over the v dd and temperature range that is expected for the application. osc1 osc2 open clock from ext. system pic18fxxxx (hs mode) mux vco loop filter crystal osc osc2 osc1 pll enable f in f out sysclk phase comparator hs oscillator enable ? 4 (from configuration register 1h) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 12 ? 2002-2015 microchip technology inc. 2.4 external clock input the ec and ecio oscillator modes require an external clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset, or after an exit from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes, or to synchronize other logic. figure 2-4 shows the pin connections for the ec oscillator mode. figure 2-4: extern al clock input operation (ec configuration) the ecio oscillator mode functions like the ec mode, except that the osc2 pin becomes an additional gen- eral purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-5 shows the pin connections for the ecio oscillator mode. figure 2-5: extern al clock input operation (ecio configuration) 2.5 rc oscillator for timing insensitive applications, the rc and rcio device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) val- ues and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. furthermore, the dif- ference in lead frame capacitance between package types will also affect the oscillation frequency, espe- cially for low c ext values. the user also needs to take into account variation, due to tolerance of external r and c components used. figure 2-6 shows how the r/c combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes, or to synchronize other logic. figure 2-6: rc oscillator mode the rcio oscillator mode ( figure 2-7 ) functions like the rc mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-7: rcio oscillator mode osc1/clki osc2/clko f osc /4 clock from ext. system pic18fxxxx osc1/clki i/o (osc2) ra6 clock from ext. system pic18fxxxx osc2/clko c ext r ext pic18fxxxx osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? ? r ext ? 100 k ? c ext > 20 pf c ext r ext pic18fxxxx osc1 internal clock v dd v ss recommended values: 3 k ? ? r ext ? 100 k ? c ext > 20 pf i/o (osc2) ra6 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 13 pic18f1220/1320 2.6 internal oscillator block the pic18f1220/1320 devices include an internal oscillator block, which generates two different clock signals; either can be used as the systems clock source. this can eliminate the need for external oscillator circuits on the osc1 and/or osc2 pins. the main output (intosc) is an 8 mhz clock source, which can be used to directly drive the system clock. it also drives a postscaler, which can provide a range of clock frequencies from 125 khz to 4 mhz. the intosc output is enabled when a system clock frequency from 125 khz to 8 mhz is selected. the other clock source is the internal rc oscillator (intrc), which provides a 31 khz output. the intrc oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled: power-up timer fail-safe clock monitor watchdog timer two-speed start-up these features are discussed in greater detail in section 19.0 ?special features of the cpu? . the clock source frequency (intosc direct, intrc direct or intosc postscaler) is selected by configuring the ircf bits of the osccon register ( register 2-2 ). 2.6.1 intio modes using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital i/o. two distinct configurations are available: in intio1 mode, the osc2 pin outputs f osc /4, while osc1 functions as ra7 for digital input and output. in intio2 mode, osc1 functions as ra7 and osc2 functions as ra6, both for digital input and output. 2.6.2 intrc output frequency the internal oscillator block is calibrated at the factory to produce an intosc output frequency of 8.0 mhz (see tab le 2 2- 6 ). this changes the frequency of the intrc source from its nominal 31.25 khz. peripherals and features that depend on the intrc source will be affected by this shift in frequency. once set during factory calibration, the intrc frequency will remain within 2% as temperature and v dd change across their full specified operating ranges. 2.6.3 osctune register the internal oscillators output has been calibrated at the factory, but can be adjusted in the users applica- tion. this is done by writing to the osctune register ( register 2-1 ). the tuning sensitivity is constant throughout the tuning range. when the osctune register is modified, the intosc and intrc frequencies will begin shifting to the new frequency. the intrc clock will reach the new frequency within 8 clock cycles (approximately 8*32 ? s = 256 ? s). the intosc clock will stabilize within 1 ms. code execution continues during this shift. there is no indication that the shift has occurred. operation of features that depend on the intrc clock source frequency, such as the wdt, fail-safe clock monitor and peripherals, will also be affected by the change in frequency. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 14 ? 2002-2015 microchip technology inc. 2.7 clock sources and oscillator switching like previous pic18 devices, the pic18f1220/1320 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. pic18f1220/ 1320 devices offer two alternate clock sources. when enabled, these give additional options for switching to the various power managed operating modes. essentially, there are three clock sources for these devices: primary oscillators secondary oscillators internal oscillator block the primary oscillators include the external crystal and resonator modes, the external rc modes, the external clock modes and the internal oscillator block. the particular mode is defined on por by the contents of configuration register 1h. the details of these modes are covered earlier in this chapter. the secondary oscillators are those external sources not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power managed mode. pic18f1220/1320 devices offer only the timer1 oscillator as a secondary oscillator. this oscillator, in all power managed modes, is often the time base for functions such as a real-time clock. most often, a 32.768 khz watch crystal is connected between the rb6/t1oso and rb7/t1osi pins. like the lp mode oscillator circuit, loading capacitors are also connected from each pin to ground. these pins are also used during icsp operations. the timer1 oscillator is discussed in greater detail in section 12.2 ?timer1 oscillator? . in addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. the intrc source is also used as the clock source for several special features, such as the wdt and fail-safe clock monitor. the clock sources for the pic18f1220/1320 devices are shown in figure 2-8 . see section 12.0 ?timer1 module? for further details of the timer1 oscillator. see section 19.1 ?configuration bits? for configuration register details. register 2-1: osctune: osci llator tuning register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tun<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 tun<5:0>: frequency tuning bits 100000 = minimum frequency 111111 = 000000 = oscillator module is running at the factory-calibrated frequency 000001 = 011110 = 011111 = maximum frequency downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 15 pic18f1220/1320 2.7.1 oscillator control register the osccon register ( register 2-2 ) controls several aspects of the system clocks operation, both in full- power operation and in power managed modes. the system clock select bits, scs1:scs0, select the clock source that is used when the device is operating in power managed modes. the available clock sources are the primary clock (defined in configuration register 1h), the secondary clock (timer1 oscillator) and the internal oscillator block. the clock selection has no effect until a sleep instruction is executed and the device enters a power managed mode of operation. the scs bits are cleared on all forms of reset. the internal oscillator select bits, ircf2:ircf0, select the frequency output of the internal oscillator block that is used to drive the system clock. the choices are the intrc source, the intosc source (8 mhz), or one of the six frequencies derived from the intosc posts- caler (125 khz to 4 mhz). if the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the inter- nal oscillators output. the osts, iofs and t1run bits indicate which clock source is currently providing the system clock. the osts indicates that the oscillator start-up timer has timed out and the primary clock is providing the system clock in primary clock modes. the iofs bit indicates when the internal oscillator block has stabilized and is providing the system clock in rc clock modes or during two-speed start-ups. the t1run bit (t1con<6>) indicates when the timer1 oscillator is providing the system clock in secondary clock modes. in power managed modes, only one of these three bits will be set at any time. if none of these bits are set, the intrc is providing the system clock, or the internal oscillator block has just started and is not yet stable. the idlen bit controls the selective shutdown of the controllers cpu in power managed modes. the uses of these bits are discussed in more detail in section 3.0 ?power managed modes? . figure 2-8: pic18f1220/1320 clock diagram note 1: the timer1 oscillator must be enabled to select the secondary clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control reg- ister (t1con<3>). if the timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a sleep instruction will be ignored. 2: it is recommended that the timer1 oscil- lator be operating and stable before exe- cuting the sleep instruction or a very long delay may occur while the timer1 oscillator starts. pic18f1220/1320 4 x pll config1h <3:0> secondary oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep primary oscillator hspll lp, xt, hs, rc, ec t1osc cpu peripherals idlen postscaler mux mux 8 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111110 101 100 011 010 001 000 31 khz intrc source internal oscillator block wdt, fscm 8 mhz internal oscillator (intosc) osccon<6:4> clock control osccon<1:0> downloaded from: http:///
pic18f1220/1320 ds30009605g-page 16 ? 2002-2015 microchip technology inc. register 2-2: osccon: os cillator control register r/w-0/0 r/w-0/0 r/w-1/1 r/w-1/1 r (1) r-0/0 r/w-0/0 r/w-0/0 idlen ircf<2:0> osts iofs scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 idlen: idle enable bits 1 = idle mode enabled; cpu core is not clocked in power managed modes 0 = run mode enabled; cpu core is clocked in run modes, but not sleep mode bit 6-4 ircf<2:0>: internal oscillator frequency select bits 111 = 8 mhz (8 mhz source drives clock directly) 110 = 4 mhz 101 = 2 mhz 100 = 1 mhz 011 = 500 khz 010 = 250 khz 001 = 125 khz 000 = 31 khz (intrc source drives clock directly) bit 3 osts: oscillator start-up time-out status bit 1 = oscillator start-up timer time-out has expired; primary oscillator is running 0 = oscillator start-up timer time-out is running; primary oscillator is not ready bit 2 iofs: intosc frequency stable bit 1 = intosc frequency is stable 0 = intosc frequency is not stable bit 1-0 scs<1:0>: system clock select bits (1) 1x = internal oscillator block (rc modes) 01 =timer1 oscillator (secondary modes) 00 = primary oscillator (sleep and pri_idle modes) note 1: depends on state of the ieso bit in configuration register 1h. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 17 pic18f1220/1320 2.7.2 oscillator transitions the pic18f1220/1320 devices contain circuitry to prevent clocking glitches when switching between clock sources. a short pause in the system clock occurs during the clock switch. the length of this pause is between eight and nine clock periods of the new clock source. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. clock transitions are discussed in greater detail in section 3.1.2 ?entering power managed modes? . 2.8 effects of power managed modes on the various clock sources when the device executes a sleep instruction, the system is switched to one of the power managed modes, depending on the state of the idlen and scs1:scs0 bits of the osccon register. see section 3.0 ?power managed modes? for details. when pri_idle mode is selected, the designated pri- mary oscillator continues to run without interruption. for all other power managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin, if used by the oscillator) will stop oscillating. in secondary clock modes (sec_run and sec_i- dle), the timer1 oscillator is operating and providing the system clock. the timer1 oscillator may also run in all power managed modes if required to clock timer1 or timer3. in internal oscillator modes (rc_run and rc_idle), the internal oscillator block provides the system clock source. the intrc output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the power managed mode (see section 19.2 ?watchdog timer (wdt)? through section 19.4 ?fail-safe clock monitor? ). the intosc output at 8 mhz may be used directly to clock the system, or may be divided down first. the intosc output is disabled if the system clock is provided directly from the intrc output. if the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. the timer1 oscillator may be operating to support a real- time clock. other features may be operating that do not require a system clock source (i.e., intn pins, a/d conversions and others). 2.9 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most applica- tions. the delays ensure that the device is kept in reset until the device power supply is stable under nor- mal circumstances and the primary clock is operating and stable. for additional information on power-up delays, see sections 4.1 through 4.5 . the first timer is the power-up timer (pwrt), which provides a fixed delay on power-up (parameter 33, table 22-8 ) if enabled in configuration register 2l. the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable (lp, xt and hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. when the hspll oscillator mode is selected, the device is kept in reset for an additional 2 ms following the hs mode ost delay, so the pll can lock to the incoming clock frequency. there is a delay of 5 to 10 ? s following por while the controller becomes ready to execute instructions. this delay runs concurrently with any other delays. this may be the only delay that occurs when any of the ec, rc or intio modes are used as the primary clock source. table 2-3: osc1 and osc2 pin states in sleep mode oscillator mode osc1 pin osc2 pin rc, intio1 floating, external resistor should pull high at logic low (clock/4 output) rcio, intio2 floating, external resistor should pull high configured as porta, bit 6 ecio floating, pulled by external clock configured as porta, bit 6 ec floating, pulled by external clock at logic low (clock/4 output) lp, xt and hs feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 4-1 in section 4.0 ?reset? for time-outs due to sleep and mclr reset. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 18 ? 2002-2015 microchip technology inc. 3.0 power managed modes the pic18f1220/1320 devices offer a total of six oper- ating modes for more efficient power management (see tab l e 3 - 1 ). these provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery powered devices). there are three categories of power managed modes: sleep mode idle modes run modes these categories define which portions of the device are clocked and sometimes, what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or intosc multiplexer); the sleep mode does not use a clock source. the clock switching feature offered in other pic18 devices (i.e., using the timer1 oscillator in place of the primary oscillator) and the sleep mode offered by all pic ? devices (where all system clocks are stopped) are both offered in the pic18f1220/1320 devices (sec_run and sleep modes, respectively). however, additional power managed modes are available that allow the user greater flexibility in determining what portions of the device are operating. the power man- aged modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these operating modes. for pic18f1220/1320 devices, the power managed modes are invoked by using the existing sleep instruction. all modes exit to pri_run mode when trig- gered by an interrupt, a reset or a wdt time-out (pri_run mode is the normal full-power execution mode; the cpu and peripherals are clocked by the pri- mary oscillator source). in addition, power managed run modes may also exit to sleep mode, or their corresponding idle mode. 3.1 selecting power managed modes selecting a power managed mode requires deciding if the cpu is to be clocked or not and selecting a clock source. the idlen bit controls cpu clocking, while the scs1:scs0 bits select a clock source. the individual modes, bit settings, clock sources and affected modules are summarized in ta b l e 3 - 1 . 3.1.1 clock sources the clock source is selected by setting the scs bits of the osccon register ( register 2-2 ). three clock sources are available for use in power managed idle modes: the primary clock (as configured in configuration register 1h), the secondary clock (timer1 oscillator) and the internal oscillator block. the secondary and internal oscillator block sources are available for the power managed modes (pri_run mode is the normal full-power execution mode; the cpu and peripherals are clocked by the primary oscillator source). table 3-1: power managed modes mode osccon bits module clocking available clock and oscillator source idlen <7> scs1:scs0 <1:0> cpu peripherals sleep 00 0 off off none C all clocks are disabled pri_run 00 0 clocked clocked primary C lp, xt , hs, hspll, rc, ec, intrc (1) this is the normal full-power execution mode. sec_run 00 1 clocked clocked secondary C timer1 oscillator rc_run 01 x clocked clocked internal oscillator block (1) pri_idle 10 0 off clocked primary C lp, xt, hs, hspll, rc, ec sec_idle 10 1 off clocked secondary C timer1 oscillator rc_idle 11 x off clocked internal oscillator block (1) note 1: includes intosc and intosc postsc aler, as well as the intrc source. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 19 pic18f1220/1320 3.1.2 entering power managed modes in general, entry, exit and switching between power managed clock sources requires clock source switching. in each case, the sequence of events is the same. any change in the power managed mode begins with loading the osccon register and executing a sleep instruction. the scs1:scs0 bits select one of three power managed clock sources; the primary clock (as defined in configuration register 1h), the secondary clock (the timer1 oscillator) and the internal oscillator block (used in rc modes). modifying the scs bits will have no effect until a sleep instruction is executed. entry to the power managed mode is triggered by the execution of a sleep instruction. figure 3-5 shows how the system is clocked while switching from the primary clock to the timer1 oscilla- tor. when the sleep instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. eight clock cycles from the new clock source are counted to synchronize with the new clock source. after eight clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. the actual length of the pause is between eight and nine clock periods from the new clock source. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. three bits indicate the current clock source: osts and iofs in the osccon register and t1run in the t1con register. only one of these bits will be set while in a power managed mode. when the osts bit is set, the primary clock is providing the system clock. when the iofs bit is set, the intosc output is providing a stable 8 mhz clock source and is providing the system clock. when the t1run bit is set, the timer1 oscillator is providing the system clock. if none of these bits are set, then either the intrc clock source is clocking the system, or the intosc source is not yet stable. if the internal oscillator block is configured as the pri- mary clock source in configuration register 1h, then both the osts and iofs bits may be set when in pri_run or pri_idle modes. this indicates that the primary clock (intosc output) is generating a stable 8 mhz output. entering an rc power managed mode (same frequency) would clear the osts bit. 3.1.3 multiple sleep commands the power managed mode that is invoked with the sleep instruction is determined by the settings of the idlen and scs bits at the time the instruction is exe- cuted. if another sleep instruction is executed, the device will enter the power managed mode specified by these same bits at that time. if the bits have changed, the device will enter the new power managed mode specified by the new bit settings. 3.1.4 comparisons between run and idle modes clock source selection for the run modes is identical to the corresponding idle modes. when a sleep instruc- tion is executed, the scs bits in the osccon register are used to switch to a different clock source. as a result, if there is a change of clock source at the time a sleep instruction is executed, a clock switch will occur. in idle modes, the cpu is not clocked and is not run- ning. in run modes, the cpu is clocked and executing code. this difference modifies the operation of the wdt when it times out. in idle modes, a wdt time-out results in a wake from power managed modes. in run modes, a wdt time-out results in a wdt reset (see table 3-2 ). during a wake-up from an idle mode, the cpu starts executing code by entering the corresponding run mode until the primary clock becomes ready. when the primary clock becomes ready, the clock source is auto- matically switched to the primary clock. the idlen and scs bits are unchanged during and after the wake-up. figure 3-2 shows how the system is clocked during the clock source switch. the example assumes the device was in sec_idle or sec_run mode when a wake is triggered (the primary clock was configured in hspll mode). note 1: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated. 2: executing a sleep instruction does not necessarily place the device into sleep mode; executing a sleep instruction is simply a trigger to place the controller into a power managed mode selected by the osccon register, one of which is sleep mode. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 20 ? 2002-2015 microchip technology inc. 3.2 sleep mode the power managed sleep mode in the pic18f1220/ 1320 devices is identical to that offered in all other pic microcontrollers. it is entered by clearing the idlen and scs1:scs0 bits (this is the reset state) and executing the sleep instruction. this shuts down the primary oscillator and the osts bit is cleared (see figure 3-1 ). when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the system will not be clocked until the primary clock source becomes ready (see figure 3-2 ), or it will be clocked from the internal oscillator block if either the two-speed start-up or the fail-safe clock monitor are enabled (see section 19.0 ?special features of the cpu? ). in either case, the osts bit is set when the primary clock is providing the system clocks. the idlen and scs bits are not affected by the wake-up. 3.3 idle modes the idlen bit allows the microcontrollers cpu to be selectively shut down while the peripherals continue to operate. clearing idlen allows the cpu to be clocked. setting idlen disables clocks to the cpu, effectively stopping program execution (see register 2-2 ). the peripherals continue to be clocked regardless of the setting of the idlen bit. there is one exception to how the idlen bit functions. when all the low-power osccon bits are cleared (idlen:scs1:scs0 = 000 ), the device enters sleep mode upon the execution of the sleep instruction. this is both the reset state of the osccon register and the setting that selects sleep mode. this maintains compatibility with other pic devices that do not offer power managed modes. if the idle enable bit, idlen (osccon<7>), is set to a 1 when a sleep instruction is executed, the peripherals will be clocked from the clock source selected using the scs1:scs0 bits; however, the cpu will not be clocked. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out or a reset. when a wake event occurs, cpu execution is delayed approximately 10 ? s while it becomes ready to execute code. when the cpu begins executing code, it is clocked by the same clock source as was selected in the power managed mode (i.e., when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals until the primary clock source becomes ready C this is essentially rc_run mode). this continues until the primary clock source becomes ready. when the primary clock becomes ready, the osts bit is set and the system clock source is switched to the primary clock (see figure 3-4 ). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to full-power operation. table 3-2: comparison between power managed modes power managed mode cpu is clocked by ... wdt time-out causes a ... peripherals are clocked by ... clock during wake-up (while primary becomes ready) sleep not clocked (not running) wake-up not clocked none or intosc multiplexer if two-speed start-up or fail-safe clock monitor are enabled any idle mode not clocked (not running) wake-up primary, secondary or intosc multiplexer unchanged from idle mode (cpu operates as in corresponding run mode) any run mode primary or secondary clocks or intosc multiplexer reset primary or secondary clocks or intosc multiplexer unchanged from run mode downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 21 pic18f1220/1320 figure 3-1: timing transiti on for entry to sleep mode figure 3-2: transition timing for wake from sleep (hspll) q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 8 pc + 6 q1 q2 q3 q4 wake event note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 4 pc + 2 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 22 ? 2002-2015 microchip technology inc. 3.3.1 pri_idle mode this mode is unique among the three low-power idle modes, in that it does not disable the primary system clock. for timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to warm up or transition from another oscillator. pri_idle mode is entered by setting the idlen bit, clearing the scs bits and executing a sleep instruc- tion. although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified in configuration register 1h. the osts bit remains set in pri_idle mode (see figure 3-3 ). when a wake event occurs, the cpu is clocked from the primary clock source. a delay of approximately 10 ? s is required between the wake event and code execution starts. this is required to allow the cpu to become ready to execute instructions. after the wake- up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 3-4 ). figure 3-3: transition timing to pri_idle mode figure 3-4: transition timing for wake from pri_idle mode q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock pc + 2 q1 q3 q4 clock counter q2 wake event cpu start-up delay downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 23 pic18f1220/1320 3.3.2 sec_idle mode in sec_idle mode, the cpu is disabled, but the peripherals continue to be clocked from the timer1 oscillator. this mode is entered by setting the idle bit, modifying bits, scs1:scs0 = 01 and executing a sleep instruction. when the clock source is switched (see figure 3-5 ) to the timer1 oscillator, the primary oscillator is shut down, the osts bit is cleared and the t1run bit is set. when a wake event occurs, the peripherals continue to be clocked from the timer1 oscillator. after a 10 ? s delay following the wake event, the cpu begins exe- cuting code, being clocked by the timer1 oscillator. the microcontroller operates in sec_run mode until the primary clock becomes ready. when the primary clock becomes ready, a clock switchback to the primary clock occurs (see figure 3-6 ). when the clock switch is com- plete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up. the timer1 oscillator continues to run. figure 3-5: timing transition for entry to sec_idle mode figure 3-6: timing transition fo r wake from sec_run mode (hspll) note: the timer1 oscillator should already be running prior to entering sec_idle mode. if the t1oscen bit is not set when the sleep instruction is executed, the sleep instruction will be ignored and entry to sec_idle mode will not occur. if the timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable oper- ation may result. q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 12345678 clock transition q1 q3 q4 osc1 peripheral program pc pc + 2 t1osi pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t pll (1) 12 3 45678 clock transition osts bit set t ost (1) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 24 ? 2002-2015 microchip technology inc. 3.3.3 rc_idle mode in rc_idle mode, the cpu is disabled, but the periph- erals continue to be clocked from the internal oscillator block using the intosc multiplexer. this mode allows for controllable power conservation during idle periods. this mode is entered by setting the idlen bit, setting scs1 (scs0 is ignored) and executing a sleep instruction. the intosc multiplexer may be used to select a higher clock frequency by modifying the ircf bits before executing the sleep instruction. when the clock source is switched to the intosc multiplexer (see figure 3-7 ), the primary oscillator is shut down and the osts bit is cleared. if the ircf bits are set to a non-zero value (thus, enabling the intosc output), the iofs bit becomes set after the intosc output becomes stable, in about 1 ms. clocks to the peripherals continue while the intosc source stabilizes. if the ircf bits were previously at a non-zero value before the sleep instruction was executed and the intosc source was already stable, the iofs bit will remain set. if the ircf bits are all clear, the intosc output is not enabled and the iofs bit will remain clear; there will be no indication of the current clock source. when a wake event occurs, the peripherals continue to be clocked from the intosc multiplexer. after a 10 ? s delay following the wake event, the cpu begins exe- cuting code, being clocked by the intosc multiplexer. the microcontroller operates in rc_run mode until the primary clock becomes ready. when the primary clock becomes ready, a clock switchback to the primary clock occurs (see figure 3-8 ). when the clock switch is complete, the iofs bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake- up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-7: timing tran sition to rc_idle mode figure 3-8: timing transition for wake from rc_run mode (rc_run to pri_run) q4 q3 q2 osc1 peripheral program q1 intrc q1 counter clock cpu clock pc + 2 pc 12345678 clock transition q1 q3 q4 osc1 peripheral program pc pc + 2 intosc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t ost (1) t pll (1) 12345678 clock transition osts bit set multiplexer q4 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 25 pic18f1220/1320 3.4 run modes if the idlen bit is clear when a sleep instruction is executed, the cpu and peripherals are both clocked from the source selected using the scs1:scs0 bits. while these operating modes may not afford the power conservation of idle or sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source. rc_run mode also offers the possibility of executing code at a frequency greater than the primary clock. wake-up from a power managed run mode can be triggered by an interrupt, or any reset, to return to full- power operation. as the cpu is executing code in run modes, several additional exits from run modes are possible. they include exit to sleep mode, exit to a cor- responding idle mode and exit by executing a reset instruction. while the device is in any of the power managed run modes, a wdt time-out will result in a wdt reset. 3.4.1 pri_run mode the pri_run mode is the normal full-power execution mode. if the sleep instruction is never executed, the microcontroller operates in this mode (a sleep instruc- tion is executed to enter all other power managed modes). all other power managed modes exit to pri_run mode when an interrupt or wdt time-out occur. there is no entry to pri_run mode. the osts bit is set. the iofs bit may be set if the internal oscillator block is the primary clock source (see section 2.7.1 ?oscillator control register? ). 3.4.2 sec_run mode the sec_run mode is the compatible mode to the clock switching feature offered in other pic18 devices. in this mode, the cpu and peripherals are clocked from the timer1 oscillator. this gives users the option of lower power consumption while still using a high accuracy clock source. sec_run mode is entered by clearing the idlen bit, setting scs1:scs0 = 01 and executing a sleep instruction. the system clock source is switched to the timer1 oscillator (see figure 3-9 ), the primary oscilla- tor is shut down, the t1run bit (t1con<6>) is set and the osts bit is cleared. when a wake event occurs, the peripherals and cpu continue to be clocked from the timer1 oscillator while the primary clock is started. when the primary clock becomes ready, a clock switchback to the primary clock occurs (see figure 3-6 ). when the clock switch is com- plete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up. the timer1 oscillator continues to run. firmware can force an exit from sec_run mode. by clearing the t1oscen bit (t1con<3>), an exit from sec_run back to normal full-power operation is trig- gered. the timer1 oscillator will continue to run and provide the system clock, even though the t1oscen bit is cleared. the primary clock is started. when the primary clock becomes ready, a clock switchback to the primary clock occurs (see figure 3-6 ). when the clock switch is complete, the timer1 oscillator is disabled, the t1run bit is cleared, the osts bit is set and the pri- mary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up. figure 3-9: timing transition for entry to sec_run mode note: the timer1 oscillator should already be running prior to entering sec_run mode. if the t1oscen bit is not set when the sleep instruction is executed, the sleep instruction will be ignored and entry to sec_run mode will not occur. if the timer1 oscillator is enabled, but not yet running, system clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 12345678 clock transition q4 q3 q2 q1 q3 q2 pc + 2 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 26 ? 2002-2015 microchip technology inc. 3.4.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator block using the intosc multiplexer and the primary clock is shut down. when using the intrc source, this mode pro- vides the best power conservation of all the run modes, while still executing code. it works well for user applications which are not highly timing sensitive, or do not require high-speed clocks at all times. if the primary clock source is the internal oscillator block (either of the intio1 or intio2 oscillators), there are no distinguishable differences between pri_run and rc_run modes during execution. however, a clock switch delay will occur during entry to and exit from rc_run mode. therefore, if the primary clock source is the internal oscillator block, the use of rc_run mode is not recommended. this mode is entered by clearing the idlen bit, setting scs1 (scs0 is ignored) and executing a sleep instruction. the ircf bits may select the clock frequency before the sleep instruction is executed. when the clock source is switched to the intosc multiplexer (see figure 3-10 ), the primary oscillator is shut down and the osts bit is cleared. the ircf bits may be modified at any time to immedi- ately change the system clock speed. executing a sleep instruction is not required to select a new clock frequency from the intosc multiplexer. if the ircf bits are all clear, the intosc output is not enabled and the iofs bit will remain clear; there will be no indication of the current clock source. the intrc source is providing the system clocks. if the ircf bits are changed from all clear (thus, enabling the intosc output), the iofs bit becomes set after the intosc output becomes stable. clocks to the system continue while the intosc source stabilizes, in approximately 1 ms. if the ircf bits were previously at a non-zero value before the sleep instruction was executed and the intosc source was already stable, the iofs bit will remain set. when a wake event occurs, the system continues to be clocked from the intosc multiplexer while the primary clock is started. when the primary clock becomes ready, a clock switch to the primary clock occurs (see figure 3-8 ). when the clock switch is complete, the iofs bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-10: timing transition to rc_run mode note: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated. q3 q2 q1 osc1 peripheral program q4 intrc q4 counter clock cpu clock pc + 2 pc 12345678 clock transition q3 q2 q1 q4 q2 q1 q3 pc + 4 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 27 pic18f1220/1320 3.4.4 exit to idle mode an exit from a power managed run mode to its corresponding idle mode is executed by setting the idlen bit and executing a sleep instruction. the cpu is halted at the beginning of the instruction following the sleep instruction. there are no changes to any of the clock source status bits (osts, iofs or t1run). while the cpu is halted, the peripherals continue to be clocked from the previously selected clock source. 3.4.5 exit to sleep mode an exit from a power managed run mode to sleep mode is executed by clearing the idlen and scs1:scs0 bits and executing a sleep instruction. the code is no different than the method used to invoke sleep mode from the normal operating (full-power) mode. the primary clock and internal oscillator block are disabled. the intrc will continue to operate if the wdt is enabled. the timer1 oscillator will continue to run, if enabled in the t1con register ( register 12-1 ). all clock source status bits are cleared (osts, iofs and t1run). 3.5 wake from power managed modes an exit from any of the power managed modes is trig- gered by an interrupt, a reset or a wdt time-out. this section discusses the triggers that cause exits from power managed modes. the clocking subsystem actions are discussed in each of the power managed modes (see sections 3.2 through 3.4 ). device behavior during low-power mode exits is summarized in ta b l e 3 - 3 . 3.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit a power managed mode and resume full- power operation. to enable this functionality, an inter- rupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. on all exits from low-power mode by interrupt, code execution branches to the interrupt vector if the gie/gieh bit (intcon<7>) is set. otherwise, code execution continues or resumes without branching (see section 9.0 ?interrupts? ). note: if application code is timing sensitive, it should wait for the osts bit to become set before continuing. use the interval during the low-power exit sequence (before osts is set) to perform timing insensitive housekeeping tasks. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 28 ? 2002-2015 microchip technology inc. table 3-3: activity and exit delay on wa ke from sleep mode or any idle mode (by clock sources) clock in power managed mode primary system clock power managed mode exit delay clock ready status bit (osccon) activity during wake-up from power managed mode exit by interrupt exit by reset primary system clock (pri_idle mode) lp, xt, hs 5-10 ? s (5) osts cpu and peripherals clocked by primary clock and executing instructions. not clocked or two-speed start-up (if enabled) (3) . hspll ec, rc, intrc (1) intosc (2) iofs t1osc or intrc (1) lp, xt, hs ost osts cpu and peripherals clocked by selected power managed mode clock and executing instructions until primary clock source becomes ready. hspll ost + 2 ms ec, rc, intrc (1) 5-10 ? s (5) intosc (2) 1ms (4) iofs intosc (2) lp, xt, hs ost osts hspll ost + 2 ms ec, rc, intrc (1) 5-10 ? s (5) intosc (2) none iofs sleep mode lp, xt, hs ost osts not clocked or two-speed start-up (if enabled) until primary clock source becomes ready (3) . hspll ost + 2 ms ec, rc, intrc (1) 5-10 ? s (5) intosc (2) 1ms (4) iofs note 1: in this instance, refers specifically to the intrc clock source. 2: includes both the intosc 8 mhz source and postscaler derived frequencies. 3: two-speed start-up is covered in greater detail in section 19.3 ?two-speed start-up? . 4: execution continues during the intosc stabilization period. 5: required delay when waking from sleep and all idle modes. this delay runs concurrently with any other required delays (see section 3.3 ?idle modes? ). downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 29 pic18f1220/1320 3.5.2 exit by reset normally, the device is held in reset by the oscillator start-up timer (ost) until the primary clock (defined in configuration register 1h) becomes ready. at that time, the osts bit is set and the device begins executing code. code execution can begin before the primary clock becomes ready. if either the two-speed start-up (see section 19.3 ?two-speed start-up? ) or fail-safe clock monitor (see section 19.4 ?fail-safe clock monitor? ) are enabled in configuration register 1h, the device may begin execution as soon as the reset source has cleared. execution is clocked by the intosc multiplexer driven by the internal oscillator block. since the osccon register is cleared following all resets, the intrc clock source is selected. a higher speed clock may be selected by modifying the ircf bits in the osccon register. execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. 3.5.3 exit by wdt time-out a wdt time-out will cause different actions, depending on which power managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in a wake from the power managed mode (see sections 3.2 through 3.4 ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 19.2 ?watchdog timer (wdt)? ). the wdt timer and postscaler are cleared by executing a sleep or clrwdt instruction, the loss of a currently selected clock source (if the fail-safe clock monitor is enabled) and modifying the ircf bits in the osccon register if the internal oscillator block is the system clock source. 3.5.4 exit without an oscillator start-up delay certain exits from power managed modes do not invoke the ost at all. these are: pri_idle mode, where the primary clock source is not stopped; or the primary clock source is not any of lp, xt, hs or hspll modes. in these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (pri_idle), or normally does not require an oscillator start-up delay (rc, ec and intio oscillator modes). however, a fixed delay (approximately 10 ? s) following the wake event is required when leaving sleep and idle modes. this delay is required for the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. 3.6 intosc frequency drift the factory calibrates the internal oscillator block output (intosc) for 8 mhz (see tab le 2 2- 6 ). however, this frequency may drift as v dd or temperature changes, which can affect the controller operation in a variety of ways. it is possible to adjust the intosc frequency by modifying the value in the osctune register ( register 2-1 ). this has the side effect that the intrc clock source frequency is also affected. however, the features that use the intrc source often do not require an exact frequency. these features include the fail-safe clock monitor, the watchdog timer and the rc_run/ rc_idle modes when the intrc clock source is selected. being able to adjust the intosc requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. three examples follow but other techniques may be used. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 30 ? 2002-2015 microchip technology inc. 3.6.1 example C eusart an adjustment may be indicated when the eusart begins to generate framing errors, or receives data with errors while in asynchronous mode. framing errors indicate that the system clock frequency is too high C try decrementing the value in the osctune register to reduce the system clock frequency. errors in data may suggest that the system clock speed is too low C increment osctune. 3.6.2 example C timers this technique compares system clock speed to some reference clock. two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the timer1 oscillator. both timers are cleared, but the timer clocked by the reference generates interrupts. when an interrupt occurs, the internally clocked timer is read and both timers are cleared. if the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast C decrement osctune. 3.6.3 example C ccp in capture mode a ccp module can use free running timer1 (or timer3), clocked by the internal oscillator block and an external event with a known period (i.e., ac power frequency). the time of the first event is captured in the ccprxh:ccprxl registers and is recorded for use later. when the second event causes a capture, the time of the first event is subtracted from the time of the second event. since the period of the external event is known, the time difference between events can be calculated. if the measured time is much greater than the calculated time, the internal oscillator block is running too fast C decrement osctune. if the measured time is much less than the calculated time, the internal oscillator block is running too slowCincrement osctune. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 31 pic18f1220/1320 4.0 reset the pic18f1220/1320 devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during execution) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a reset state, depending on the type of reset that occurred. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. status bits from the rcon register ( register 5-2 ), ri , to , pd , por and bor , are set or cleared differently in different reset situations, as indicated in ta b l e 4 - 2 . these bits are used in software to determine the nature of the reset. see table 4-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 4-1 . the enhanced mcu devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. the mclr pin is not driven low by any internal resets, including the wdt. the mclr input provided by the mclr pin can be disabled with the mclre bit in configuration register 3h (config3h<7>). figure 4-1: simplified block di agram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt time-out v dd rise detect ost/pwrt intrc (1) por pulse ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter enable ost (2) enable pwrt note 1: this is a separate oscillator from the rc oscillator of the clki pin. 2: see table 4-1 for time-out situations. brown-out reset bor reset instruction stack pointer stack full/underflow reset sleep ( )_idle 1024 cycles 65.5 ms 32 ? s mclre downloaded from: http:///
pic18f1220/1320 ds30009605g-page 32 ? 2002-2015 microchip technology inc. 4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected. to take advantage of the por circuitry, just tie the mclr pin through a resistor (1k to 10 k ? ) to v dd . this will eliminate external rc compo- nents usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 4-2 . when the device starts normal operation (i.e., exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. figure 4-2: exte rnal power-on reset circuit (for slow v dd power-up) 4.2 power-up timer (pwrt) the power-up timer (pwrt) of the pic18f1220/1320 is an 11-bit counter, which uses the intrc source as the clock input. this yields a count of 2048 x 32 ? s=65.6ms. while the pwrt is counting, the device is held in reset. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see dc parameter 33 for details. the pwrt is enabled by clearing configuration bit, pwrten . 4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter 33). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp, hs and hspll modes and only on power-on reset, or on exit from most low-power modes. 4.4 pll lock time-out with the pll enabled in its pll mode, the time-out sequence following a power-on reset is slightly different from other oscillator modes. a portion of the power-up timer is used to provide a fixed time-out that is sufficient for the pll to lock to the main oscillator fre- quency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out. 4.5 brown-out reset (bor) a configuration bit, bor, can disable (if clear/ programmed), or enable (if set) the brown-out reset circuitry. if v dd falls below v bor (parameter d005) for greater than t bor (parameter 35), the brown-out situa- tion will reset the chip. a reset may not occur if v dd falls below v bor for less than t bor . the chip will remain in brown-out reset until v dd rises above v bor . if the power-up timer is enabled, it will be invoked after v dd rises above v bor ; it then will keep the chip in reset for an additional time delay, t pwrt (parameter 33). if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initial- ized. once v dd rises above v bor , the power-up timer will execute the additional time delay. enabling bor reset does not automatically enable the pwrt. 4.6 time-out sequence on power-up, the time-out sequence is as follows: first, after the por pulse has cleared, pwrt time-out is invoked (if enabled). then, the ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 4-3 , figure 4-4 , figure 4-5 , figure 4-6 and figure 4-7 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, all time-outs will expire. bring- ing mclr high will begin execution immediately ( figure 4-5 ). this is useful for testing purposes or to synchronize more than one pic18fxxxx device operating in parallel. table 4-2 shows the reset conditions for some special function registers, while tab l e 4 - 3 shows the reset conditions for all the registers. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the devices electric al specification. 3: r1 ? 1 k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr/ v pp pin breakdown due to electro- static discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18fxxxx v dd downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 33 pic18f1220/1320 table 4-1: time-out in various situations table 4-2: status bits, their significanc e and the initialization condition for rcon register oscillator configuration power-up (2) and brown-out exit from low-power mode pwrten = 0 pwrten = 1 hspll 66 ms (1) + 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) hs, xt, lp 66 ms (1) + 1024 t osc 1024 t osc 1024 t osc ec, ecio 66 ms (1) 5-10 ? s (3) 5-10 ? s (3) rc, rcio 66 ms (1) 5-10 ? s (3) 5-10 ? s (3) intio1, intio2 66 ms (1) 5-10 ? s (3) 5-10 ? s (3) note 1: 66 ms (65.5 ms) is the nominal power-up timer (pwrt) delay. 2: 2 ms is the nominal time required for the 4x pll to lock. 3: the program memory bias start-up time is always invoked on por, wake-up from sleep, or on any exit from power managed mode that disables the cpu and instruction execution. register 4-1: osccon: os cillator control register r/w-0/0 u-0 u-0 r/w-1/1 r/w-1/1 u-0 r/w-1/1 r/w-1/1 ipen r i to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared note: refer to section 5.14 ?rcon register? for bit definitions. condition program counter rcon register ri to pd por bor stkful stkunf power-on reset 0000h 0--1 1100 1 11 0 00 0 reset instruction 0000h 0--0 uuuu 0 uu u uu u brown-out 0000h 0--1 11u- 1 1 1 u 0u u mclr during power managed run modes 0000h 0--u 1uuu u 1 u u uu u mclr during power managed idle modes and sleep 0000h 0--u 10uu u 1 0 u uu u wdt time-out during full-power or power managed run 0000h 0--u 0uuu u 0u u uu u mclr during full-power execution 0000h 0--u uuuu u u u u u uu stack full reset (stvr = 1 ) 1u stack underflow reset (stvr = 1 ) u1 stack underflow error (not an actual reset, stvr = 0 ) 0000h u--u uuuu u u u u u u 1 wdt time-out during power man- aged idle or sleep pc + 2 u--u 00uu u 00 u uu u interrupt exit from power managed modes pc + 2 u--u u0uu u u0 u uu u legend: u = unchanged, x = unknown, C = unimplemented bit, read as 0 note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector (0x000008h or 0x000018h). downloaded from: http:///
pic18f1220/1320 ds30009605g-page 34 ? 2002-2015 microchip technology inc. table 4-3: initialization co nditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu 1220 1320 ---0 0000 ---0 0000 ---0 uuuu (3) tosh 1220 1320 0000 0000 0000 0000 uuuu uuuu (3) tosl 1220 1320 0000 0000 0000 0000 uuuu uuuu (3) stkptr 1220 1320 00-0 0000 00-0 0000 uu-u uuuu (3) pclatu 1220 1320 ---0 0000 ---0 0000 ---u uuuu pclath 1220 1320 0000 0000 0000 0000 uuuu uuuu pcl 1220 1320 0000 0000 0000 0000 pc + 2 (2) tblptru 1220 1320 --00 0000 --00 0000 --uu uuuu tblptrh 1220 1320 0000 0000 0000 0000 uuuu uuuu tblptrl 1220 1320 0000 0000 0000 0000 uuuu uuuu tablat 1220 1320 0000 0000 0000 0000 uuuu uuuu prodh 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu prodl 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu intcon 1220 1320 0000 000x 0000 000u uuuu uuuu (1) intcon2 1220 1320 1111 -1-1 1111 -1-1 uuuu -u-u (1) intcon3 1220 1320 11-0 0-00 11-0 0-00 uu-u u-uu (1) indf0 1220 1320 n/a n/a n/a postinc0 1220 1320 n/a n/a n/a postdec0 1220 1320 n/a n/a n/a preinc0 1220 1320 n/a n/a n/a plusw0 1220 1320 n/a n/a n/a fsr0h 1220 1320 ---- 0000 ---- 0000 ---- uuuu fsr0l 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu wreg 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu indf1 1220 1320 n/a n/a n/a postinc1 1220 1320 n/a n/a n/a postdec1 1220 1320 n/a n/a n/a preinc1 1220 1320 n/a n/a n/a plusw1 1220 1320 n/a n/a n/a fsr1h 1220 1320 ---- 0000 ---- 0000 ---- uuuu fsr1l 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-2 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read 0 . 6: bit 5 of porta is enabled if mclr is disabled. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 35 pic18f1220/1320 bsr 1220 1320 ---- 0000 ---- 0000 ---- uuuu indf2 1220 1320 n/a n/a n/a postinc2 1220 1320 n/a n/a n/a postdec2 1220 1320 n/a n/a n/a preinc2 1220 1320 n/a n/a n/a plusw2 1220 1320 n/a n/a n/a fsr2h 1220 1320 ---- 0000 ---- 0000 ---- uuuu fsr2l 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu status 1220 1320 ---x xxxx ---u uuuu ---u uuuu tmr0h 1220 1320 0000 0000 0000 0000 uuuu uuuu tmr0l 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu t0con 1220 1320 1111 1111 1111 1111 uuuu uuuu osccon 1220 1320 0000 q000 0000 q000 uuuu qquu lvdcon 1220 1320 --00 0101 --00 0101 --uu uuuu wdtcon 1220 1320 ---- ---0 ---- ---0 ---- ---u rcon (4) 1220 1320 0--1 11q0 0--q qquu u--u qquu tmr1h 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu t1con 1220 1320 0000 0000 u0uu uuuu uuuu uuuu tmr2 1220 1320 0000 0000 0000 0000 uuuu uuuu pr2 1220 1320 1111 1111 1111 1111 1111 1111 t2con 1220 1320 -000 0000 -000 0000 -uuu uuuu adresh 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu adresl 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 1220 1320 00-0 0000 00-0 0000 uu-u uuuu adcon1 1220 1320 -000 0000 -000 0000 -uuu uuuu adcon2 1220 1320 0-00 0000 0-00 0000 u-uu uuuu ccpr1h 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 1220 1320 0000 0000 0000 0000 uuuu uuuu pwm1con 1220 1320 0000 0000 0000 0000 uuuu uuuu eccpas 1220 1320 0000 0000 0000 0000 uuuu uuuu table 4-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-2 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read 0 . 6: bit 5 of porta is enabled if mclr is disabled. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 36 ? 2002-2015 microchip technology inc. tmr3h 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu t3con 1220 1320 0-00 0000 u-uu uuuu u-uu uuuu spbrgh 1220 1320 0000 0000 0000 0000 uuuu uuuu spbrg 1220 1320 0000 0000 0000 0000 uuuu uuuu rcreg 1220 1320 0000 0000 0000 0000 uuuu uuuu txreg 1220 1320 0000 0000 0000 0000 uuuu uuuu txsta 1220 1320 0000 0010 0000 0010 uuuu uuuu rcsta 1220 1320 0000 000x 0000 000x uuuu uuuu baudctl 1220 1320 -1-1 0-00 -1-1 0-00 -u-u u-uu eeadr 1220 1320 0000 0000 0000 0000 uuuu uuuu eedata 1220 1320 0000 0000 0000 0000 uuuu uuuu eecon2 1220 1320 0000 0000 0000 0000 0000 0000 eecon1 1220 1320 xx-0 x000 uu-0 u000 uu-0 u000 ipr2 1220 1320 1--1 -11- 1--1 -11- u--u -uu- pir2 1220 1320 0--0 -00- 0--0 -00- u--u -uu- (1) pie2 1220 1320 0--0 -00- 0--0 -00- u--u -uu- ipr1 1220 1320 -111 -111 -111 -111 -uuu -uuu pir1 1220 1320 -000 -000 -000 -000 -uuu -uuu (1) pie1 1220 1320 -000 -000 -000 -000 -uuu -uuu osctune 1220 1320 --00 0000 --00 0000 --uu uuuu trisb 1220 1320 1111 1111 1111 1111 uuuu uuuu trisa (5) 1220 1320 11-1 1111 (5) 11-1 1111 (5) uu-u uuuu (5) latb 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) 1220 1320 xx-x xxxx (5) uu-u uuuu (5) uu-u uuuu (5) portb 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu porta (5,6) 1220 1320 xx0x 0000 (5,6) uu0u 0000 (5,6) uuuu uuuu (5,6) table 4-3: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0 , q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-2 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read 0 . 6: bit 5 of porta is enabled if mclr is disabled. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 37 pic18f1220/1320 figure 4-3: time-out sequ ence on power-up (mclr tied to v dd , v dd rise < t pwrt ) figure 4-4: time-out sequ ence on power-up (mclr not tied to v dd ): case 1 figure 4-5: time-out sequ ence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost downloaded from: http:///
pic18f1220/1320 ds30009605g-page 38 ? 2002-2015 microchip technology inc. figure 4-6: slow rise time (mclr tied to v dd , v dd r ise > t pwrt ) figure 4-7: time-out sequence on por w/pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll ? 2 ms max. first three stages of the pwrt timer. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 39 pic18f1220/1320 5.0 memory organization there are three memory types in enhanced mcu devices. these memory types are: program memory data ram data eeprom data and program memory use separate busses, which allows for concurrent access of these types. additional detailed information for flash program mem- ory and data eeprom is provided in section 6.0 ?flash program memory? and section 7.0 ?data eeprom memory? , respectively. figure 5-1: program memory map and stack for pic18f1220 5.1 program memory organization a 21-bit program counter is capable of addressing the 2-mbyte program memory space. accessing a location between the physically implemented memory and the 2-mbyte address will cause a read of all 0 s (a nop instruction). the pic18f1220 has 4 kbytes of flash memory and can store up to 2,048 single-word instructions. the pic18f1320 has 8 kbytes of flash memory and can store up to 4,096 single-word instructions. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. the program memory maps for the pic18f1220 and pic18f1320 devices are shown in figure 5-1 and figure 5-2 , respectively. figure 5-2: program memory map and stack for pic18f1320 pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ?? call,rcall,return retfie,retlw 21 0000h0018h on-chip program memory high priority interrupt vector 0008h user memory space 1fffffh 1000h 0fffh read ? 0 ? 200000h pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ?? call,rcall,return retfie,retlw 21 0000h0018h 2000h 1fffh on-chip program memory high priority interrupt vector 0008h user memory space read ? 0 ? 1fffffh 200000h downloaded from: http:///
pic18f1220/1320 ds30009605g-page 40 ? 2002-2015 microchip technology inc. 5.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (program counter) is pushed onto the stack when a call or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return , retlw or a retfie instruction. pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, with the stack pointer initialized to 00000 b after all resets. there is no ram associated with stack pointer, 00000 b . this is only a reset value. during a call type instruction, causing a push onto the stack, the stack pointer is first incremented and the ram location pointed to by the stack pointer (stkptr) register is written with the contents of the pc (already pointing to the instruction following the call) . during a return type instruction, causing a pop from the stack, the contents of the ram location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack special file registers. data can also be pushed to or popped from the stack using the top-of-stack sfrs. status bits indicate if the stack is full, has overflowed or underflowed. 5.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosu, tosh and tosl, hold the contents of the stack location pointed to by the stkptr register ( figure 5-3 ). this allows users to implement a software stack if necessary. after a call , rcall or interrupt, the software can read the pushed value by reading the tosu, tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosu, tosh and tosl and do a return. the user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. 5.2.2 return stack pointer (stkptr) the stkptr register ( register 5-1 ) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. at reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvr (stack overflow reset enable) configuration bit. (refer to section 19.1 ?configuration bits? for a description of the device configuration bits.) if stvr is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvr is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software or a por occurs. figure 5-3: return address stack and associated registers note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. 00011 001a34h 1111111110 11101 00010 00001 00000 00010 return address stack top-of-stack 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 41 pic18f1220/1320 5.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the cur- rent pc value onto the stack. tosu, tosh and tosl can then be modified to place data or a return address on the stack. the ability to pull the tos value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the pop instruction. the pop instruc- tion discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. 5.2.4 stack full/underflow resets these resets are enabled by programming the stvr bit in configuration register 4l. when the stvr bit is cleared, a full or underflow condition will set the appro- priate stkful or stkunf bit, but not cause a device reset. when the stvr bit is set, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. the stkful or stkunf bits are cleared by the user software or a power-on reset. register 5-1: stkptr: stack pointer register r/c-0/0 r/c-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 stkful (1) stkunf (1) sp<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared c = clearable only bit bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as 0 bit 4-0 sp<4:0>: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 42 ? 2002-2015 microchip technology inc. 5.3 fast register stack a fast return option is available for interrupts. a fast register stack is provided for the status, wreg and bsr registers and is only one in depth. the stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. the values in the registers are then loaded back into the working registers, if the retfie, fast instruction is used to return from the interrupt. all interrupt sources will push values into the stack registers. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. if a high priority inter- rupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. users must save the key registers in software during a low priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label, fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return, fast instruction is then executed to restore these registers from the fast register stack. example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. example 5-1: fast register stack code example 5.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits and is not directly readable or writable. updates to the pch register may be per- formed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits and is not directly readable or writable. updates to the pcu register may be performed through the pclatu register. the contents of pclath and pclatu will be transferred to the program counter by any operation that writes pcl. similarly, the upper two bytes of the program counter will be transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 5.8.1 ?computed goto? ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of pcl is fixed to a value of 0 . the pc increments by two to address sequential instructions in the program memory. the call , rcall , goto and program branch instruc- tions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ?? sub1 ?? return, fast ;restore values saved ;in fast register stack downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 43 pic18f1220/1320 5.5 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 5-4 . 5.6 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction ( example 5-2 ). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 5-4: clock/ instruction cycle example 5-2: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc C 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock all instructions are single cycle, except for any program branches. these take two cy cles, since the fetch instruction is flushed from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 44 ? 2002-2015 microchip technology inc. 5.7 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). figure 5-5 shows an example of how instruction words are stored in the pro- gram memory. to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read 0 (see section 5.4 ?pcl, pclath and pclatu? ). the call and goto instructions have the absolute program memory address embedded into the instruc- tion. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 5-5 shows how the instruction goto 000006h is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction represents the number of single-word instructions that the pc will be offset by. section 20.0 ?instruction set summary? provides further details of the instruction set. figure 5-5: instructions in program memory 5.7.1 two-word instructions pic18f1220/1320 devices have four two-word instructions: movff , call , goto and lfsr . the second word of these instructions has the 4 msbs set to 1 s and is decoded as a nop instruction. the lower 12 bits of the second word contain data to be used by the instruction. if the first word of the instruction is executed, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip operation. a program example that demonstrates this concept is shown in example 5-3 . refer to section 20.0 ?instruction set summary? for further details of the instruction set. example 5-3: two- word instructions word address lsb = 1 lsb = 0 ? program memory byte locations ? ? 000000h000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 000006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h000014h case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 45 pic18f1220/1320 5.8 look-up tables look-up tables are implemented two ways: computed goto table reads 5.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter (see example 5-4 ). a look-up table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw 0xnn instructions, that returns the value 0xnn to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 5-4: computed goto using an offset value 5.8.2 table reads/table writes a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored two bytes per pro- gram word by using table reads and writes. the table pointer (tblptr) register specifies the byte address and the table latch (tablat) register contains the data that is read from or written to program memory. data is transferred to/from program memory, one byte at a time. the table read/table write operation is discussed further in section 6.1 ?table reads and table writes? . 5.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. figure 5-6 shows the data memory organization for the pic18f1220/1320 devices. the data memory map is divided into as many as 16 banks that contain 256 bytes each. the lower four bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper four bits for the bsr are not implemented. the data memory contains special function registers (sfr) and general purpose registers (gpr). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratch pad operations in the users appli- cation. the sfrs start at the last location of bank 15 (fffh) and extend towards f80h. any remaining space beyond the sfrs in the bank may be implemented as gprs. gprs start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as 0 s. the entire data memory may be accessed directly or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of a file select register (fsrn) and a corresponding indi- rect file operand (indfn). each fsr holds a 12-bit address value that can be used to access any location in the data memory map without banking. see section 5.12 ?indirect addressing, indf and fsr registers? for indirect addressing details. the instruction set and architecture allow operations across all banks. this may be accomplished by indirect addressing or by the use of the movff instruction. the movff instruction is a two-word/two-cycle instruction that moves a value from one register to another. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access ram. section 5.10 ?access bank? provides a detailed description of the access ram. 5.9.1 general purpose register file enhanced mcu devices may have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as gpr registers by all instructions. the second half of bank 15 (f80h to fffh) contains sfrs. all other banks of data memory contain gprs, starting with bank 0. movfw offset call table org 0xnn00 table addwf pcl retlw 0xnn retlw 0xnn retlw 0xnn . . . downloaded from: http:///
pic18f1220/1320 ds30009605g-page 46 ? 2002-2015 microchip technology inc. figure 5-6: data memory map for pic18f1220/1320 devices bank 0 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 1111 080h 07fh f80h fffh 00h 7fh 80h ffh access bank when a = 0 , the bsr is ignored and the access bank is used. the first 128 bytes are general purpose ram (from bank 0). the second 128 bytes are special function registers (from bank 15). when a = 1 , the bsr specifies the bank used by the instruction. f7fh f00h effh 0ffh 000h access ram ffh 00h ffh 00h gpr sfr unused access ram high access ram low bank 1 to unused read 00h = 1110 = 0001 (sfrs) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 47 pic18f1220/1320 5.9.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in ta b l e 5 - 1 and tab l e 5 - 2 . the sfrs can be classified into two sets: those asso- ciated with the core function and those related to the peripheral functions. those registers related to the core are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfrs are typically distributed among the peripherals whose functions they control. the unused sfr locations will be unimplemented and read as 0 s. table 5-1: special function register map for pic18f1220/1320 devices address name address name address name address name fffh tosu fdfh indf2 (2) fbfh ccpr1h f9fh ipr1 ffeh tosh fdeh postinc2 (2) fbeh ccpr1l f9eh pir1 ffdh tosl fddh postdec2 (2) fbdh ccp1con f9dh pie1 ffch stkptr fdch preinc2 (2) fbch f9ch ffbh pclatu fdbh plusw2 (2) fbbh f9bh osctune ffah pclath fdah fsr2h fbah f9ah ff9h pcl fd9h fsr2l fb9h f99h ff8h tblptru fd8h status fb8h f98h ff7h tblptrh fd7h tmr0h fb7h pwm1con f97h ff6h tblptrl fd6h tmr0l fb6h eccpas f96h ff5h tablat fd5h t0con fb5h f95h ff4h prodh fd4h fb4h f94h ff3h prodl fd3h osccon fb3h tmr3h f93h trisb ff2h intcon fd2h lvdcon fb2h tmr3l f92h trisa ff1h intcon2 fd1h wdtcon fb1h t3con f91h ff0h intcon3 fd0h rcon fb0h spbrgh f90h fefh indf0 (2) fcfh tmr1h fafh spbrg f8fh feeh postinc0 (2) fceh tmr1l faeh rcreg f8eh fedh postdec0 (2) fcdh t1con fadh txreg f8dh fech preinc0 (2) fcch tmr2 fach txsta f8ch febh plusw0 (2) fcbh pr2 fabh rcsta f8bh feah fsr0h fcah t2con faah baudctl f8ah latb fe9h fsr0l fc9h fa9h eeadr f89h lata fe8h wreg fc8h fa8h eedata f88h fe7h indf1 (2) fc7h fa7h eecon2 f87h fe6h postinc1 (2) fc6h fa6h eecon1 f86h fe5h postdec1 (2) fc5h fa5h f85h fe4h preinc1 (2) fc4h adresh fa4h f84h fe3h plusw1 (2) fc3h adresl fa3h f83h fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb fe0h bsr fc0h adcon2 fa0h pie2 f80h porta note 1: unimplemented registers are read as 0 . 2: this is not a physical register. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 48 ? 2002-2015 microchip technology inc. table 5-2: register file summary (pic18f1220/1320) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: tosu top-of-stack upper byte (tos<20:16>) ---0 0000 34, 40 tosh top-of-stack high byte (tos<15:8>) 0000 0000 34, 40 tosl top-of-stack low byte (tos<7:0>) 0000 0000 34, 40 stkptr stkful stkunf return stack pointer 00-0 0000 34, 41 pclatu b i t 2 1 (3) holding register for pc<20:16> ---0 0000 34, 42 pclath holding register for pc<15:8> 0000 0000 34, 42 pcl pc low byte (pc<7:0>) 0000 0000 34, 42 tblptru bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 34, 58 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 34, 58 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 34, 58 tablat program memory table latch 0000 0000 34, 58 prodh product register high byte xxxx xxxx 34, 68 prodl product register low byte xxxx xxxx 34, 68 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 34, 72 intcon2 rbpu intedg0 intedg1 intedg2 t m r 0 i p r b i p 1111 -1-1 34, 73 intcon3 int2ip int1ip i n t 2 i ei n t 1 i e int2if int1if 11-0 0-00 34, 74 indf0 uses contents of fsr0 to address data memory C value of fsr0 not changed (not a physical reg ister) n/a 34, 51 postinc0 uses contents of fsr0 to address data memory C value of fsr0 post-i ncremented (not a physical register) n/a 34, 51 postdec0 uses contents of fsr0 to address data memoryC value of fsr0 post-decremented (not a physical register) n/a 34, 51 preinc0 uses contents of fsr0 to address data memory C value of fsr0 pre-incremented (not a physical register) n/a 34, 51 plusw0 uses contents of fsr0 to address data memory C value of fsr0 offset b y w (not a physical register) n/a 34, 51 fsr0h indirect data memory address pointer 0 high ---- 0000 34, 51 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 34, 51 wreg working register xxxx xxxx 34 indf1 uses contents of fsr1 to address data memory C value of fsr1 not changed (not a physical reg ister) n/a 34, 51 postinc1 uses contents of fsr1 to address data memory C value of fsr1 post-i ncremented (not a physical register) n/a 34, 51 postdec1 uses contents of fsr1 to address data memory C value of fsr1 post-decre mented (not a physical register) n/a 34, 51 preinc1 uses contents of fsr1 to address data memory C value of fsr1 pre-incremented (not a physical register) n/a 34, 51 plusw1 uses contents of fsr1 to address data memory C value of fsr1 offset b y w (not a physical register) n/a 34, 51 fsr1h indirect data memory address pointer 1 high ---- 0000 34, 51 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 34, 51 bsr bank select register ---- 0000 35, 50 indf2 uses contents of fsr2 to address data memory C value of fsr2 not changed (not a physical reg ister) n/a 35, 51 postinc2 uses contents of fsr2 to address data memory C value of fsr2 post-i ncremented (not a physical register) n/a 35, 51 postdec2 uses contents of fsr2 to address data memory C value of fsr2 post-decre mented (not a physical register) n/a 35, 51 preinc2 uses contents of fsr2 to address data memory C value of fsr2 pre-incremented (not a physical register) n/a 35, 51 plusw2 uses contents of fsr2 to address data memory C value of fsr2 offset b y w (not a physical register) n/a 35, 51 fsr2h indirect data memory address pointer 2 high ---- 0000 35, 51 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 35, 51 status no vzd cc ---x xxxx 35, 53 tmr0h timer0 register high byte 0000 0000 35, 97 tmr0l timer0 register low byte xxxx xxxx 35, 97 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 35, 95 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0000 q000 35, 16 lvdcon ivrst lvden lvdl3 lvdl2 lvdl1 lvdl0 --00 0101 35, 162 wdtcon s w d t e n --- ---0 35, 174 rcon ipen r i to pd por bor 0--1 11q0 33, 54, 81 legend: x = unknown, u = unchanged, C = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio, ecio and intio2 (with port func tion on ra6) oscillator mode only a nd read 0 in all other oscillator modes. 2: ra7 and associated bits are configured as port pins in intio2 oscillator mode on ly and read 0 in all other modes. 3: bit 21 of the pc is only available in test mode and serial programming modes. 4: the ra5 port bit is only available when mclre fuse (config3h<7>) is programmed to 0 . otherwise, ra5 reads 0 . this bit is read-only. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 49 pic18f1220/1320 tmr1h timer1 register high byte xxxx xxxx 35, 103 tmr1l timer1 register low byte xxxx xxxx 35, 103 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 35, 98 tmr2 timer2 register 0000 0000 35, 104 pr2 timer2 period register 1111 1111 35, 104 t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 35, 104 adresh a/d result register high byte xxxx xxxx 35, 159 adresl a/d result register low byte xxxx xxxx 35, 159 adcon0 vcfg1 vcfg0 chs2 chs1 chs0 go/done adon 00-0 0000 35, 150 adcon1 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 -000 0000 35, 151 adcon2 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 35, 152 ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx 35. 110 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx 35, 110 ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 35, 109 pwm1con prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 0000 0000 35, 121 eccpas eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 35, 122 tmr3h timer3 register high byte xxxx xxxx 36, 108 tmr3l timer3 register low byte xxxx xxxx 36, 108 t3con rd16 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0-00 0000 36, 106 spbrgh eusart baud rate generator high byte 0000 0000 36 spbrg eusart baud rate generator low byte 0000 0000 36, 130 rcreg eusart receive register 0000 0000 36, 138, 137 txreg eusart transmit register 0000 0000 36, 135, 137 txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 36, 127 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 36, 128 baudctl rcidl s c k pb r g 1 6 wue abden -1-1 0-00 36, 129 eeadr eeprom address register 0000 0000 36, 64 eedata eeprom data register 0000 0000 36, 67 eecon2 eeprom control register 2 (not a physical register) 0000 0000 36, 56, 64 eecon1 eepgd cfgs free wrerr wren wr rd xx-0 x000 36, 57, 65 ipr2 oscfip e e i p lvdip tmr3ip 1--1 -11- 36, 80 pir2 oscfif eeif l v d i ft m r 3 i f 0--0 -00- 36, 76 pie2 oscfie e e i e lvdie tmr3ie 0--0 -00- 36, 78 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 36, 79 pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 36, 75 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 36, 77 osctune tun5 tun4 tun3 tun2 tun1 tun0 --00 0000 36, 14 trisb data direction control register for portb 1111 1111 36, 94 trisa trisa7 (2) trisa6 (1) data direction control register for porta 11-1 1111 36, 85 latb read/write portb data latch xxxx xxxx 36, 94 lata lata<7> (2) lata<6> (1) read/write porta data latch xx-x xxxx 36, 85 portb read portb pins, write portb data latch xxxx xxxx 36, 94 porta ra7 (2) ra6 (1) ra5 (4) read porta pins, write porta data latch xx0x 0000 36, 85 table 5-2: register file summary (pic18f1220/1320) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, C = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio, ecio and intio2 (with port fun ction on ra6) oscillator mode only a nd read 0 in all other oscillator modes. 2: ra7 and associated bits are configured as port pins in intio2 oscillator mode on ly and read 0 in all other modes. 3: bit 21 of the pc is only available in test mode and serial programming modes. 4: the ra5 port bit is only available when mclre fuse (config3h<7>) is programmed to 0 . otherwise, ra5 reads 0 . this bit is read-only. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 50 ? 2002-2015 microchip technology inc. 5.10 access bank the access bank is an architectural enhancement which is very useful for c compiler code optimization. the techniques used by the c compiler may also be useful for programs written in assembly. this data memory region can be used for: intermediate computational values local variables of subroutines faster context saving/switching of variables common variables faster evaluation/control of sfrs (no banking) the access bank is comprised of the last 128 bytes in bank 15 (sfrs) and the first 128 bytes in bank 0. these two sections will be referred to as access ram high and access ram low, respectively. figure 5-6 indicates the access ram areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register or in the access bank. this bit is denoted as the a bit (for access bit). when forced in the access bank (a = 0 ), the last address in access ram low is followed by the first address in access ram high. access ram high maps the special function registers, so these registers can be accessed without any software overhead. this is useful for testing status flags and modifying control bits. 5.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. the data memory is partitioned into as many as sixteen banks. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper four bits of the 12-bit ram address. the bsr<7:4> bits will always read 0 s and writes will have no effect (see figure 5-7 ). a movlb instruction has been provided in the instruction set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all 0 s and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr, since the 12-bit addresses are embedded into the instruction word. section 5.12 ?indirect addressing, indf and fsr registers? provides a description of indirect address- ing, which allows linear addressing of the entire ram space. figure 5-7: direct addressing note 1: for register file map detail, see table 5-1 . 2: the access bit of the instruction can be used to force an ov erride of the selected bank (bsr<3:0>) to the registers of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory (1) direct addressing bank select (2) location select (3) bsr<3:0> 7 0 from opcode (3) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h effh e00h fffh f00h bsr<7:4> 0000 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 51 pic18f1220/1320 5.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. an fsr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modified by the program. this can be useful for data tables in the data memory and for software stacks. figure 5-8 shows how the fetched instruction is modified prior to being executed. indirect addressing is possible by using one of the indf registers. any instruction, using the indf regis- ter, actually accesses the register pointed to by the file select register, fsr. reading the indf register itself, indirectly (fsr = 0 ), will read 00h. writing to the indf register indirectly, results in a no operation ( nop ). the fsr register contains a 12-bit address, which is shown in figure 5-9 . the indfn register is not a physical register. address- ing indfn actually addresses the register whose address is contained in the fsrn register (fsrn is a pointer). this is indirect addressing. example 5-5 shows a simple use of indirect addressing to clear the ram in bank 1 (locations 100h-1ffh) in a minimum number of instructions. example 5-5: how to clear ram (bank 1) using indirect addressing there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12-bit wide. to store the 12 bits of addressing information, two 8-bit registers are required: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing, with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address pointed to by fsr0h:fsr0l. a read from indf1 reads the data from the address pointed to by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1 or indf2 are read indirectly via an fsr, all 0 s are read (zero bit is set). similarly, if indf0, indf1 or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 5.12.1 indirect addressing operation each fsr register has an indf register associated with it, plus four additional register addresses. performing an operation using one of thes e five registers determines how the fsr will be modified during indirect addressing. when data access is performed using one of the five indfn locations, the address selected will configure the fsrn register to: do nothing to fsrn after an indirect access (no change) C indfn auto-decrement fsrn after an indirect access (post-decrement) C postdecn auto-increment fsrn after an indirect access (post-increment) C postincn auto-increment fsrn before an indirect access (pre-increment) C preincn use the value in the wreg register as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) C pluswn when using the auto-increment or auto-decrement features, the effect on the fsr is not reflected in the status register. for example, if the indirect address causes the fsr to equal 0 , the z bit will not be set. auto-incrementing or auto-decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a stack pointer, in addition to its uses for table operations in data memory. each fsr has an address associated with it that performs an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the signed value in the wreg register and the value in fsr to form the address before an indirect access. the fsr value is not changed. the wreg offset range is -128 to +127. if an fsr register contains a value that points to one of the indfn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a nop (status bits are not affected). if an indirect addressing write is performed when the tar- get address is an fsrnh or fsrnl register, the data is written to the fsr register, but no pre- or post-increment/ decrement is performed. lfsr fsr0,0x100 ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? goto next ; no, clear next continue ; yes, continue downloaded from: http:///
pic18f1220/1320 ds30009605g-page 52 ? 2002-2015 microchip technology inc. figure 5-8: indirect addressing operation figure 5-9: indirect addressing opcode address file address = access of an indirect addressing register fsr instruction executed instruction fetched ram opcode file 12 12 12 bsr<3:0> 8 4 0h fffh note 1: for register file map detail, see table 5-1 . data memory (1) indirect addressing fsrnh:fsrnl 30 0fffh 0000h location select 11 0 07 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 53 pic18f1220/1320 5.13 status register the status register, shown in register 5-2 , contains the arithmetic status of the alu. as with any other sfr, it can be the operand for any instruction. if the status register is the destination for an instruc- tion that affects the z, dc, c, ov or n bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed. there- fore, the result of an instruction with the status register as its destination may be different than intended. as an example, clrf status will set the z bit and leave the remaining status bits unchanged ( 000u u1uu ). it is recommended that only bcf , bsf , swapf , movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions that do not affect status bits, see the instruction set summaries in ta b l e 2 0 - 1 . note: the c and dc bits operate as the borrow and digit borrow bits, respectively, in subtraction. register 5-2: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u no v z d cc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as 0 bit 4 n: negative bit this bit is used for signed arithmetic (2s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2s complement). it indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 54 ? 2002-2015 microchip technology inc. 5.14 rcon register the reset control (rcon) register contains flag bits that allow differentiation between the sources of a device reset. these flags include the to , pd , por , bor and ri bits. this register is readable and writable. note 1: if the bor configuration bit is set (brown-out reset enabled), the bor bit is 1 on a power-on reset. after a brown-out reset has occurred, the bor bit will be cleared and must be set by firmware to indicate the occurrence of the next brown-out reset. 2: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. register 5-3: rcon: re set control register r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen r i to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as 0 bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed (set by firmware only) 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = cleared by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 55 pic18f1220/1320 6.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 8 bytes at a time. program memory is erased in blocks of 64 bytes at a time. a bulk erase operation may not be issued from user code. while writing or erasing program memory, instruction fetches cease until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 6.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: table read ( tblrd ) table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is eight bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into tablat in the data ram space. figure 6-1 shows the operation of a table read with program memory and data ram. table write operations store data from tablat in the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 6.5 ?writing to flash program memory? . figure 6-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word aligned (tblptrl<0> = 0 ). the eeprom on-chip timer controls the write and erase times. the write and erase voltages are gener- ated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. figure 6-1: tabl e read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer points to a byte in program memory. program memory (tblptr) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 56 ? 2002-2015 microchip technology inc. figure 6-2: table write operation 6.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: eecon1 register eecon2 register tablat register tblptr registers 6.2.1 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all 0 s. the eecon2 register is used exclusively in the memory write and erase sequences. control bit, eepgd, determines if the access will be to program or data eeprom memory. when clear, operations will access the data eeprom memory. when set, program memory is accessed. control bit, cfgs, determines if the access will be to the configuration registers, or to program memory/data eeprom memory. when set, subsequent operations access configuration registers. when cfgs is clear, the eepgd bit selects either program flash or data eeprom memory. the free bit controls program memory erase opera- tions. when the free bit is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit enables and disables erase and write operations. when set, erase and write operations are allowed. when clear, erase and write operations are disabled C the wr bit cannot be set while the wren bit is clear. this process helps to prevent accidental writes to memory due to errant (unexpected) code execution. firmware should keep the wren bit clear at all times, except when starting erase or write operations. once firmware has set the wr bit, the wren bit may be cleared. clearing the wren bit will not affect the operation in progress. the wrerr bit is set when a write operation is interrupted by a reset. in these situations, the user can check the wrerr bit and rewrite the location. it will be necessary to reload the data and address registers (eedata and eeadr) as these registers have cleared as a result of the reset. control bits, rd and wr, start read and erase/write operations, respectively. these bits are set by firmware and cleared by hardware at the completion of the operation. the rd bit cannot be set when accessing program memory (eepgd = 1 ). program memory is read using table read instructions. see section 6.3 ?reading the flash program memory? regarding table reads. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of eight holding registers, the address of which is determined by tblptrl<2:0>. the process for physically writing data to the program memory array is discussed in section 6.5 ?writing to flash program memory? . holding registers program memory note: interrupt flag bit, eeif in the pir2 register, is set when the write is complete. it must be cleared in software. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 57 pic18f1220/1320 register 6-1: eecon1: ee prom control 1 register r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs free wrerr (1) wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hc = bit is cleared by hardware bit 7 eepgd: flash program or data eeprom memory select bit 1 = access program flash memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = accesses configuration, user id and device id registers 0 = accesses flash program or data eeprom memory bit 5 unimplemented: read as 0 bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation C tblptr<5:0> are ignored) 0 = perform write only bit 3 wrerr: eeprom error flag bit (1) 1 = a write operation was prematurely terminated (any reset during self-timed programming) 0 = the write operation completed normally bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash and data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle completed bit 0 rd: read control bit 1 = initiates a memory read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = read completed note 1: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 58 ? 2002-2015 microchip technology inc. 6.2.2 tablat C table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch is used to hold 8-bit data during data transfers between program memory and data ram. 6.2.3 tblptr C table pointer register the table pointer (tblptr) addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. setting the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer (tblptr) register is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table operation. these operations are shown in table 6-1 . these operations on the tblptr only affect the low-order 21 bits. 6.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the table pointer determine which byte is read from program or configuration memory into tablat. when a tblwt is executed, the three lsbs of the table pointer (tblptr<2:0>) determine which of the eight program memory holding registers is written to. when the timed write to program memory (long write) begins, the 19 msbs of the table pointer (tblptr<21:3>) will determine which program memory block of 8 bytes is written to (tblptr<2:0> are ignored). for more detail, see section 6.5 ?writing to flash program memory? . when an erase of program memory is executed, the 16 msbs of the table pointer (tblptr<21:6>) point to the 64-byte block that will be erased. the least significant bits (tblptr<5:0>) are ignored. figure 6-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 6-1: table pointer operations wi th tblrd and tblwt instructions figure 6-3: table pointer bo undaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+tblwt*+ tblptr is incremented after the read/write tblrd*-tblwt*- tblptr is decremented after the read/write tblrd+*tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 erase ? tblptr<21:6> long write ? tblptr<21:3> read or write ? tblptr<21:0> tblptrl tblptrh tblptru downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 59 pic18f1220/1320 6.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and place it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing a tblrd instruction places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 6-4 shows the interface between the internal program memory and the tablat. figure 6-4: reads from flash program memory example 6-1: reading a flash program memory word odd (high) byte program memory even (low) byte tablat tblptr instruction register (ir) read register lsb = 1 tblptr lsb = 0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment tblptr movfw tablat ; get data movwf word_even tblrd*+ ; read into tablat and increment tblptr movfw tablat ; get data movwf word_odd downloaded from: http:///
pic18f1220/1320 ds30009605g-page 60 ? 2002-2015 microchip technology inc. 6.4 erasing flash program memory the minimum erase block size is 32 words or 64 bytes under firmware control. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in flash memory is not supported. when initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased. the most significant 16 bits of the tblptr<21:6> point to the block being erased. tblptr<5:0> are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash program memory. the cfgs bit must be clear to access program flash and data eeprom memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. the wr bit is set as part of the required instruction sequence (as shown in example 6-2 ) and starts the actual erase operation. it is not necessary to load the tablat register with any data as it is ignored. for protection, the write initiate sequence using eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 6.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer with address of row being erased. 2. set the eecon1 register for the erase operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren bit to enable writes; set free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase (about 2 ms using internal timer). 8. execute a nop . 9. re-enable interrupts. example 6-2: erasing a flash program memory row movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_row bsf eecon1, eepgd ; point to flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h movwf eecon2 ; write 55h required movlw aah sequence movwf eecon2 ; write aah bsf eecon1, wr ; start erase (cpu stall) nop bsf intcon, gie ; re-enable interrupts downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 61 pic18f1220/1320 6.5 writing to flash program memory the programming block size is 4 words or 8 bytes. word or byte programming is not supported. table writes are used internally to load the holding registers needed to program the flash memory. there are eight holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction must be executed eight times for each programming operation. all of the table write operations will essentially be short writes, because only the holding registers are written. at the end of updating eight registers, the eecon1 register must be written to, to start the programming operation with a long write. the long write is necessary for programming the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. figure 6-5: table writes to flash program memory 6.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 64 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer with address being erased. 4. do the row erase procedure (see section 6.4.1 ?flash program memory erase sequence? ). 5. load table pointer with address of first byte being written. 6. write the first 8 bytes into the holding registers with auto-increment. 7. set the eecon1 register for the write operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren bit to enable byte writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for duration of the write (about 2 ms using internal timer). 13. execute a nop . 14. re-enable interrupts. 15. repeat steps 6-14 seven times to write 64 bytes. 16. verify the memory (table read). this procedure will require about 18 ms to update one row of 64 bytes of memory. an example of the required code is given in example 6-3 . holding register tablat holding register tblptr = xxxxx7 holding register tblptr = xxxxx1 holding register tblptr = xxxxx0 8 8 8 8 write register tblptr = xxxxx2 program memory downloaded from: http:///
pic18f1220/1320 ds30009605g-page 62 ? 2002-2015 microchip technology inc. example 6-3: writing to flash program memory movlw d'64 ; number of bytes in erase block movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low ; 6 lsb = 0 movwf tblptrl read_block tblrd*+ ; read into tablat, and inc movf tablat, w ; get data movwf postinc0 ; store data and increment fsr0 decfsz counter ; done? goto read_block ; repeat modify_word movlw data_addr_high ; point to buffer movwf fsr0h movlw data_addr_low movwf fsr0l movlw new_data_low ; update buffer word and increment fsr0 movwf postinc0 movlw new_data_high ; update buffer word movwf indf0 erase_block movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low ; 6 lsb = 0 movwf tblptrl bcf eecon1, cfgs ; point to prog/eeprom memory bsf eecon1, eepgd ; point to flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h ; required sequence movwf eecon2 ; write 55h movlw aah movwf eecon2 ; write aah bsf eecon1, wr ; start erase (cpu stall) nop bsf intcon, gie ; re-enable interrupts write_buffer_back movlw 8 ; number of write buffer groups of 8 bytes movwf counter_hi movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l program_loop movlw 8 ; number of bytes in holding register movwf counter downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 63 pic18f1220/1320 example 6-3: writing to flash program memory (continued) 6.5.2 write verify depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset during normal operation. in these situations, users can check the wrerr bit and rewrite the location. 6.6 flash program operation during code protection see section 19.0 ?special features of the cpu? for details on code protection of flash program memory. table 6-2: registers associated with program flash memory write_word_to_hregs movf postinc0, w ; get low byte of buffer data and increment fsr0 movwf tablat ; present data to table latch tblwt+* ; short write ; to internal tblwt holding register, increment tblptr decfsz counter ; loop until buffers are full goto write_word_to_hregs program_memory bcf intcon, gie ; disable interrupts movlw 55h ; required sequence movwf eecon2 ; write 55h movlw aah movwf eecon2 ; write aah bsf eecon1, wr ; start program (cpu stall) nop bsf intcon, gie ; re-enable interrupts decfsz counter_hi ; loop until done goto program_loop bcf eecon1, wren ; disable write to memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets tblptru bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 --00 0000 tbpltrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 0000 0000 tblptrl program memory table pointer high byte (tblptr<7:0>) 0000 0000 0000 0000 tablat program memory table latch 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u eecon2 eeprom control register 2 (not a physical register) eecon1 eepgd cfgs free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 oscfip e e i p lvdip tmr3ip 1--1 -11- 1--1 -11- pir2 oscfif e e i f lvdif tmr3if 0--0 -00- 0--0 -00- pie2 oscfie e e i e lvdie tmr3ie 0--0 -00- 0--0 -00- legend: x = unknown, u = unchanged, C = unimplemented, read as 0 . shaded cells are not used during flash/eeprom access. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 64 ? 2002-2015 microchip technology inc. 7.0 data eeprom memory the data eeprom is readable and writable during normal operation over the entire v dd range. the data memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers (sfr). there are four sfrs used to read and write the program and data eeprom memory. these registers are: eecon1 eecon2 eedata eeadr the eeprom data memory allows byte read and write. when interfacing to the data memory block, eedata holds the 8-bit data for read/write and eeadr holds the address of the eeprom location being accessed. these devices have 256 bytes of data eeprom with an address range from 00h to ffh. the eeprom data memory is rated for high erase/ write cycle endurance. a byte write automatically erases the location and writes the new data (erase- before-write). the write time is controlled by an on-chip timer. the write time will vary with voltage and temperature, as well as from chip to chip. please refer to parameter d122 ( tab l e 2 2- 1 in section 22.0 ?electrical characteristics? ) for exact limits. 7.1 eeadr the address register can address 256 bytes of data eeprom. 7.2 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all 0 s. the eecon2 register is used exclusively in the memory write and erase sequences. control bit, eepgd, determines if the access will be to program or data eeprom memory. when clear, operations will access the data eeprom memory. when set, program memory is accessed. control bit, cfgs, determines if the access will be to the configuration registers or to program memory/data eeprom memory. when set, subsequent operations access configuration registers. when cfgs is clear, the eepgd bit selects either program flash or data eeprom memory. the wren bit enables and disables erase and write operations. when set, erase and write operations are allowed. when clear, erase and write operations are disabled C the wr bit cannot be set while the wren bit is clear. this mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution. firmware should keep the wren bit clear at all times, except when starting erase or write operations. once firmware has set the wr bit, the wren bit may be cleared. clearing the wren bit will not affect the operation in progress. the wrerr bit is set when a write operation is interrupted by a reset. in these situations, the user can check the wrerr bit and rewrite the location. it is necessary to reload the data and address registers (eedata and eeadr), as these registers have cleared as a result of the reset. control bits, rd and wr, start read and erase/write operations, respectively. these bits are set by firmware and cleared by hardware at the completion of the operation. the rd bit cannot be set when accessing program memory (eepgd = 1 ). program memory is read using table read instructions. see section 6.1 ?table reads and table writes? regarding table reads. note: interrupt flag bit, eeif in the pir2 register, is set when write is complete. it must be cleared in software. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 65 pic18f1220/1320 register 7-1: eecon1: ee prom control 1 register r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs free wrerr (1) wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hc = bit is cleared by hardware bit 7 eepgd: flash program or data eeprom memory select bit 1 = access program flash memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = accesses configuration, user id and device id registers 0 = accesses flash program or data eeprom memory bit 5 unimplemented: read as 0 bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation C tblptr<5:0> are ignored) 0 = perform write only bit 3 wrerr: eeprom error flag bit (1) 1 = a write operation was prematurely terminated (any reset during self-timed programming) 0 = the write operation completed normally bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash and data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle completed bit 0 rd: read control bit 1 = initiates a memory read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = read completed note 1: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 66 ? 2002-2015 microchip technology inc. 7.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd control bit (eecon1<7>) and then set control bit, rd (eecon1<0>). the data is available for the very next instruction cycle; therefore, the eedata register can be read by the next instruction. eedata will hold this value until another read operation, or until it is written to by the user (during a write operation). 7.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadr register and the data written to the eedata register. the sequence in example 7-2 must be followed to initiate the write cycle. the write will not begin if this sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. it is strongly recom- mended that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code exe- cution (i.e., runaway programs). the wren bit should be kept clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, eecon1, eeadr and eedata cannot be modified. the wr bit will be inhibited from being set unless the wren bit is set. the wren bit must be set on a previous instruc- tion. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the eeprom interrupt flag bit (eeif) is set. the user may either enable this interrupt or poll this bit. eeif must be cleared by software. 7.5 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 7.6 protection against spurious write there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch or software malfunction. example 7-1: data eeprom read example 7-2: data eeprom write movlw data_ee_addr; movwf eeadr ; data memory address to read bcf eecon1, eepgd; point to data memory bsf eecon1, rd ; eeprom read movf eedata, w ; w = eedata movlw data_ee_addr; movwf eeadr ; data memory address to write movlw data_ee_data; movwf eedata ; data memory value to write bcf eecon1, eepgd; point to data memory bsf eecon1, wren; enable writes bcf intcon, gie ; disable interrupts movlw 55h ; required movwf eecon2 ; write 55h sequence movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts sleep ; wait for interrupt to signal write complete bcf eecon1, wren; disable writes downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 67 pic18f1220/1320 7.7 operation during code-protect data eeprom memory has its own code-protect bits in configuration words. external read and write operations are disabled if either of these mechanisms are enabled. the microcontroller itself can both read and write to the internal data eeprom, regardless of the state of the code-protect configuration bit. refer to section 19.0 ?special features of the cpu? for additional information. 7.8 using the data eeprom the data eeprom is a high endurance, byte address- able array that has been optimized for the storage of fre- quently changing information (e.g., program variables or other data that are updated often). frequently changing values will typically be updated more often than specifi- cation d124. if this is not the case, an array refresh must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. a simple data eeprom refresh routine is shown in example 7-3 . example 7-3: data eeprom refresh routine table 7-1: registers associated with data eeprom memory note: if data eeprom is only used to store constants and/or data that changes rarely, an array refresh is likely not required. see specification d124. clrf eeadr ; start at address 0 bcf eecon1, cfgs ; set for memory bcf eecon1, eepgd ; set for data eeprom bcf intcon, gie ; disable interrupts bsf eecon1, wren ; enable writes loop ; loop to refresh array bsf eecon1, rd ; read current address movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write btfsc eecon1, wr ; wait for write to complete bra $-2 incfsz eeadr, f ; increment address bra loop ; not zero, do it again bcf eecon1, wren ; disable writes bsf intcon, gie ; enable interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u eeadr eeprom address register 0000 0000 0000 0000 eedata eeprom data register 0000 0000 0000 0000 eecon2 eeprom control register 2 (not a physical register) eecon1 eepgd cfgs free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 oscfip e e i p lvdip tmr3ip 1--1 -11- 1--1 -11- pir2 oscfif e e i f lvdif tmr3if 0--0 -00- 0--0 -00- pie2 oscfie e e i e lvdie tmr3ie 0--0 -00- 0--0 -00- legend: x = unknown, u = unchanged, C = unimplemented, read as 0 . shaded cells are not used during flash/eeprom access. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 68 ? 2002-2015 microchip technology inc. 8.0 8 x 8 hardware multiplier 8.1 introduction an 8 x 8 hardware multiplier is included in the alu of the pic18f1220/1320 devices. by making the multiply a hardware operation, it completes in a single instruc- tion cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product register pair (prodh:prodl). the multiplier does not affect any flags in the status register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algorithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 8-1 shows a performance comparison between enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply. table 8-1: performance comparison 8.2 operation example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each arguments most significant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 unsigned multiply routine example 8-2: 8 x 8 signed multiply routine routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 ? s2 7 . 6 ? s6 9 ? s hardware multiply 1 1 100 ns 400 ns 1 ? s 8 x 8 signed without hardware multiply 33 91 9.1 ? s3 6 . 4 ? s9 1 ? s hardware multiply 6 6 600 ns 2.4 ? s6 ? s 16 x 16 unsigned without hardware multiply 21 242 24.2 ? s9 6 . 8 ? s2 4 2 ? s hardware multiply 28 28 2.8 ? s1 1 . 2 ? s2 8 ? s 16 x 16 signed without hardware multiply 52 254 25.4 ? s1 0 2 . 6 ? s2 5 4 ? s hardware multiply 35 40 4 ? s1 6 ? s4 0 ? s movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 69 pic18f1220/1320 example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in four registers, res3:res0. equation 8-1: 16 x 16 unsigned multiplication algorithm example 8-3: 16 x 16 unsigned multiply routine example 8-4 shows the sequence to do a 16 x 16 signed multiply. equation 8-2 shows the algorithm used. the 32-bit result is stored in four registers, res3:res0. to account for the sign bits of the argu- ments, each argument pairs most significant bit (msb) is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm example 8-4: 16 x 16 signed multiply routine movfarg1l, w mulwfarg2l ; arg1l * arg2l -> ; prodh:prodl movffprodh, res1 ; movffprodl, res0 ; ; movfarg1h, w mulwfarg2h ; arg1h * arg2h -> ; prodh:prodl movffprodh, res3 ; movffprodl, res2 ; ; movfarg1l, w mulwfarg2h ; arg1l * arg2h -> ; prodh:prodl movfprodl, w ; addwfres1, f ; add cross movfprodh, w ; products addwfcres2, f ; clrfwreg ; addwfcres3,f ; ; movfarg1h, w ; mulwfarg2l ; arg1h * arg2l -> ; prodh:prodl movfprodl, w ; addwfres1, f ; add cross movfprodh, w ; products addwfcres2, f ; clrfwreg ; addwfcres3, f ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code : res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 70 ? 2002-2015 microchip technology inc. 9.0 interrupts the pic18f1220/1320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. high priority interrupt events will interrupt any low priority interrupts that may be in prog- ress. there are ten registers which are used to control interrupt operation. these registers are: rcon intcon intcon2 intcon3 pir1, pir2 pie1, pie2 ipr1, ipr2 it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. in general, each interrupt source has three bits to control its operation. the functions of these bits are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority (int0 has no priority bit and is always high priority) the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set (high priority). setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared (low priority). when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with pic mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit, which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit, which enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. low priority interrupts are not processed while high priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the return from interrupt instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel, if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or 2-cycle instructions. indi- vidual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control regis- ters while any interrupt is enabled. doing so may cause erratic microcontroller behavior. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 71 pic18f1220/1320 figure 9-1: interrupt logic tmr0ie gieh/gie giel/peie wake-up if in low-power mode interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip int0if int0ie rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie giel\peie interrupt to cpu vector to location ipen ipen 0018h int0if int0ie int0if int0ie adif adie adip rcif rcie rcip additional peripheral interrupts adif adie adip high priority interrupt generation low priority interrupt generation rcif rciercip additional peripheral interrupts gie\gieh downloaded from: http:///
pic18f1220/1320 ds30009605g-page 72 ? 2002-2015 microchip technology inc. 9.1 intcon registers the intcon registers are readable and writable registers, which contain various enable, priority and flag bits. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. register 9-1: intcon: interrupt control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmask ed peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt oc curred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit (1) 1 = at least one of the rb<7:4> pins changed state (must be cleared in software) 0 = none of the rb<7:4> pins have changed state note 1: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 73 pic18f1220/1320 register 9-2: intcon2: interrupt control register 2 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-1/1 u-0 r/w-1/1 rbpu intedg0 intedg1 intedg2 t m r 0 i p r b i p bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0: external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 unimplemented: read as 0 bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 =high priority 0 = low priority bit 1 unimplemented: read as 0 bit 0 rbip: rb port change interrupt priority bit 1 =high priority 0 = low priority note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 74 ? 2002-2015 microchip technology inc. register 9-3: intcon3: interrupt control register 3 r/w-1/1 r/w-1/1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 int2ip int1ip int2ie int1ie int2if int1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 unimplemented: read as 0 bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 unimplemented: read as 0 bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 75 pic18f1220/1320 9.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are two peripheral interrupt request (flag) registers (pir1, pir2). note 1: interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon<7>). 2: user software should ensure the appro- priate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. register 9-4: pir1: peripheral interrupt request register 1 u-0 r/w-0/0 r-0/0 r-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 adif rcif txif ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 =the a/d conversion is not complete bit 5 rcif: eusart receive interrupt flag bit 1 = the eusart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the eusart receive buffer is empty bit 4 txif: eusart transmit interrupt flag bit 1 = the eusart transmit buffer, txreg, is empty (cleared when txreg is w ritten) 0 = the eusart transmit buffer is full bit 3 unimplemented: read as 0 bit 2 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow downloaded from: http:///
pic18f1220/1320 ds30009605g-page 76 ? 2002-2015 microchip technology inc. register 9-5: pir2: peripheral interrupt request register 2 r/w-0/0 u-0 u-0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 oscfif eeif lvdif tmr3if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 oscfif: oscillator fail interrupt flag bit 1 = system oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = system clock operating bit 6-5 unimplemented: read as 0 bit 4 eeif: data eeprom/flash write operation interrupt flag bit 1 = the write operation is complete (must be cleared in software) 0 = the write operation is not complete or has not been started bit 3 unimplemented: read as 0 bit 2 lvdif: low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low-voltage detect trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 unimplemented: read as 0 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 77 pic18f1220/1320 9.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are two peripheral interrupt enable registers (pie1, pie2). when ipen = 0 , the peie bit must be set to enable any of these peripheral interrupts. register 9-6: pie1: peripheral interrupt enable register 1 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 adie rcie txie ccp1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie: eusart receive interrupt enable bit 1 = enables the eusart receive interrupt 0 = disables the eusart receive interrupt bit 4 txie: eusart transmit interrupt enable bit 1 = enables the eusart transmit interrupt 0 = disables the eusart transmit interrupt bit 3 unimplemented: read as 0 bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt downloaded from: http:///
pic18f1220/1320 ds30009605g-page 78 ? 2002-2015 microchip technology inc. register 9-7: pie2: peripheral interrupt enable register 2 r/w-0/0 u-0 u-0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 oscfie eeie lvdie tmr3ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 =disabled bit 6-5 unimplemented: read as 0 bit 4 eeie: data eeprom/flash write operation interrupt enable bit 1 = enabled 0 =disabled bit 3 unimplemented: read as 0 bit 2 lvdie: low-voltage detect interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 =disabled bit 0 unimplemented: read as 0 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 79 pic18f1220/1320 9.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are two peripheral interrupt priority registers (ipr1, ipr2). using the priority bits requires that the interrupt priority enable (ipen) bit be set. register 9-8: ipr1: peripheral interrupt priority register 1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 adip rcip txip ccp1ip tmr2ip tmr1ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 adip: a/d converter interrupt priority bit 1 = high priority 0 = low priority bit 5 rcip: eusart receive interrupt priority bit 1 = high priority 0 = low priority bit 4 txip: eusart transmit interrupt priority bit 1 = high priority 0 = low priority bit 3 unimplemented: read as 0 bit 2 ccp1ip: ccp1 interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 = high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 = high priority 0 = low priority downloaded from: http:///
pic18f1220/1320 ds30009605g-page 80 ? 2002-2015 microchip technology inc. register 9-9: ipr2: peripheral interrupt priority register 2 r/w-1/1 u-0 u-0 r/w-1/1 u-0 r/w-1/1 r/w-1/1 u-0 oscfip eeip lvdip tmr3ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 oscfip: oscillator fail interrupt priority bit 1 = high priority 0 = low priority bit 6-5 unimplemented: read as 0 bit 4 eeip: data eeprom/flash write operation interrupt priority bit 1 = high priority 0 = low priority bit 3 unimplemented: read as 0 bit 2 lvdip: low-voltage detect interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 = high priority 0 = low priority bit 0 unimplemented: read as 0 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 81 pic18f1220/1320 9.5 rcon register the rcon register contains bits used to determine the cause of the last reset or wake-up from a low-power mode. rcon also contains the bit that enables interrupt priorities (ipen). register 9-10: rcon: re set control register r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen r i to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as 0 bit 4 ri : reset instruction flag bit for details of bit operation, see register 5-3 . bit 3 to : watchdog time-out flag bit for details of bit operation, see register 5-3 . bit 2 pd : power-down detection flag bit for details of bit operation, see register 5-3 . bit 1 por : power-on reset status bit for details of bit operation, see register 5-3 . bit 0 bor : brown-out reset status bit for details of bit operation, see register 5-3 . downloaded from: http:///
pic18f1220/1320 ds30009605g-page 82 ? 2002-2015 microchip technology inc. 9.6 intn pin interrupts external interrupts on the rb0/int0, rb1/int1 and rb2/int2 pins are edge-triggered: either rising if the corresponding intedgx bit is set in the intcon2 reg- ister, or falling if the intedgx bit is clear. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxf, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxe. flag bit, intxf, must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1 and int2) can wake-up the processor from low-power modes if bit intxe was set prior to going into low-power modes. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1 and int2 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>) and int2ip (intcon3<7>). there is no priority bit associated with int0. it is always a high priority interrupt source. 9.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow (ffh ? 00h) in the tmr0 register will set flag bit, tmr0if. in 16-bit mode, an overflow (ffffh ?? 0000h) in the tmr0h:tmr0l registers will set flag bit, tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip (intcon2<2>). see section 11.0 ?timer0 module? for further details on the timer0 module. 9.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 9.9 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 5.3 ?fast register stack? ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service routine. depending on the users application, other registers may also need to be saved. example 9-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 9-1: saving status, wr eg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 83 pic18f1220/1320 10.0 i/o ports depending on the device selected and features enabled, there are up to five ports available. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (output latch) the data latch (lata) register is useful for read- modify-write operations on the value that the i/o pins are driving. a simplified model of a generic i/o port without the interfaces to other peripherals is shown in figure 10-1 . figure 10-1: generic i/o port operation 10.1 porta, trisa and lata registers porta is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. the data latch register (lata) is also memory mapped. read-modify-write operations on the lata register read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the sixth pin of porta (mclr /v pp /ra5) is an input only pin. its operation is controlled by the mclre configuration bit in configuration register 3h (config3h<7>). when selected as a port pin (mclre = 0 ), it functions as a digital input only pin; as such, it does not have tris or lat bits associated with its operation. otherwise, it functions as the devices master clear input. in either configuration, ra5 also functions as the programming voltage input during programming. pins ra6 and ra7 are multiplexed with the main oscil- lator pins; they are enabled as oscillator or i/o pins by the selection of the main oscillator in configuration register 1h (see section 19.1 ?configuration bits? for details). when they are not used as port pins, ra6 and ra7 and their associated tris and lat bits are read as 0 . the other porta pins are multiplexed with analog inputs, the analog v ref + and v ref - inputs and the lvd input. the operation of pins ra3:ra0 as a/d converter inputs is selected by clearing/setting the control bits in the adcon1 register (a/d control register 1). the ra4/t0cki pin is a schmitt trigger input and an open-drain output. all other porta pins have ttl input levels and full cmos output drivers. the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 10-1: initiali zing porta data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin (1) q d ck q d ck en qd en rd lat or port note 1: i/o pins have diode protection to v dd and v ss . note: on a power-on reset, ra5 is enabled as a digital input only if master clear functionality is disabled. note: on a power-on reset, ra3:ra0 are configured as analog inputs and read as 0 . ra4 is always a digital pin. clrf porta ; initialize porta by ; clearing output; data latches clrf lata ; alternate method ; to clear output; data latches movlw 0x7f ; configure a/d movwf adcon1 ; for digital inputs movlw 0xd0 ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as outputs ; ra<7:4> as inputs downloaded from: http:///
pic18f1220/1320 ds30009605g-page 84 ? 2002-2015 microchip technology inc. figure 10-2: blo ck diagram of ra3:ra0 pins figure 10-3: blo ck diagram of osc2/clko/ra6 pin figure 10-4: block diagram of ra4/t0cki pin figure 10-5: block diagram of osc1/clki/ra7 pin data bus qd en p n wr lata wr trisa data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode to a/d converter and lvd modules rd lata or porta q d q ck q d q ck schmitt trigger input buffer data bus q d q ck qd en p n wr lata wr data latch tris latch rd rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . or porta rd lata ra6 enable ecio or enable rcio trisa q d q ck trisa schmitt trigger input buffer data bus wr trisa rd porta data latch tris latch schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en rd lata wr lata or porta note 1: i/o pins have protection diodes to v dd and v ss . rd trisa data bus q d q ck qd en p n wr lata wr data latch tris latch rd rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . or porta rd lata enable ra7 trisa q d q ck trisa ra7 enable to oscillator schmitt trigger input buffer downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 85 pic18f1220/1320 figure 10-6: mclr /v pp /ra5 pin block diagram table 10-1: porta functions table 10-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit 0 st input/output port pin or analog input. ra1/an1/lvdin bit 1 st input/output port pin, analog input or low-voltage detect input. ra2/an2/v ref - bit 2 st input/output port pin, analog input or v ref -. ra3/an3/v ref + bit 3 st input/output port pin, analog input or v ref +. ra4/t0cki bit 4 st input/output port pin or external clock input for timer0. output is open-drain type. mclr /v pp /ra5 bit 5 st master clear input or programming voltage input (if mclr is enabled); input only port pin or programming voltage input (if mclr is disabled). osc2/clko/ra6 bit 6 st osc2, clock output or i/o pin. osc1/clki/ra7 bit 7 st osc1, clock input or i/o pin. legend: ttl = ttl input, st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porta ra7 (1) ra6 (1) ra5 (2) ra4 ra3 ra2 ra1 ra0 xx0x 0000 uu0u 0000 lata lata7 (1) lata6 (1) lata data output register xx-x xxxx uu-u uuuu trisa trisa7 (1) trisa6 (1) porta data direction register 11-1 1111 11-1 1111 adcon1 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 -000 0000 -000 0000 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by porta. note 1: ra7:ra6 and their associated latch and data direction bits are enabled as i/o pins based on oscillator configuration; otherwise, they are read as 0 . 2: ra5 is an input only if mclr is disabled. mclr /v pp /ra5 data bus rd porta rd lata schmitt trigger mclre rd trisa qd en latch filter low-level mclr detect high-voltage detect internal mclr hv downloaded from: http:///
pic18f1220/1320 ds30009605g-page 86 ? 2002-2015 microchip technology inc. 10.2 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register read and write the latched output value for portb. example 10-2: initializing portb pins rb0-rb2 are multiplexed with int0-int2; pins rb0, rb1 and rb4 are multiplexed with a/d inputs; pins rb1 and rb4 are multiplexed with eusart; and pins rb2, rb3, rb6 and rb7 are multiplexed with eccp. each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit, rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb7:rb4) have an interrupt- on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the mismatch outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff instruction). this will end the mismatch condition. b) clear flag bit, rbif. a mismatch condition will continue to set flag bit, rbif. reading portb will end the mismatch condition and allow flag bit, rbif, to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. figure 10-7: block diagram of rb0/an4/int0 pin note: on a power-on reset, rb4:rb0 are configured as analog inputs by default and read as 0 ; rb7:rb5 are configured as digital inputs. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0x70 ; set rb0, rb1, rb4 as movwf adcon1 ; digital i/o pins movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs data latch rbpu (2) p v dd data bus wr latb wr trisb rd trisb rd portb weak pull-up intx i/o pin (1) schmitt trigger buffer tris latch rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). to a/d converter analog input mode ttl input buffer q d ck q d ck en qd en downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 87 pic18f1220/1320 figure 10-8: block diagram of rb1/an5/tx/ck/int1 pin data latch rbpu (2) p v dd q d ck q d ck q d en data bus wr latb wr trisb rd trisb rd portb weak pull-up rd portb rb1 pin (1) tris latch rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). to a/d converter int1/ck input analog input mode 1 0 tx/ck data eusart enable schmitt trigger input buffer tx/ck tris analog input mode ttl input buffer downloaded from: http:///
pic18f1220/1320 ds30009605g-page 88 ? 2002-2015 microchip technology inc. figure 10-9: block diagra m of rb2/p1b/int2 pin data latch rbpu (2) p v dd q d ck q d ck q d en data bus wr latb or wr trisb rd trisb rd portb weak pull-up rd portb rb2 pin (1) ttl input buffer tris latch rd latb portb p1b data 1 0 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). p1b enable int2 input schmitt trigger p1b/d tri-state auto-shutdown downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 89 pic18f1220/1320 figure 10-10: block diagra m of rb3/ccp1/p1a pin data bus wr latb or wr trisb data latch tris latch rd trisb q d q ck qd en eccp1/p1a data out 1 0 q d q ck p n v dd v ss rd portb eccp1 input rb3 pin portb rd latb schmitt trigger v dd weak pull-up p rbpu (2) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). 3: eccp1 pin output enable active for any pwm mode and compare mode, where ccp1m<3:0> = 1000 or 1001 . 4: eccp1 pin input enable active for capture mode only. eccp1 (3) pin output enable p1a/c tri-state auto-shutdown eccp1 (4) pin input enable downloaded from: http:///
pic18f1220/1320 ds30009605g-page 90 ? 2002-2015 microchip technology inc. figure 10-11: block diagram of rb4/an6/rx/dt/kbi0 pin data bus wr latb or wr trisb data latch tris latch rd trisb q d q ck qd en dt data 1 0 q d q ck rd portb rb4 pin portb rd latb rbpu (2) p weak pull-up q1 from other qd en set rbif rb7:rb4 pins rd portb q3 to a/d converter eusart enabled ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). dt tris analog input mode rx/dt input analog input mode schmitt trigger v dd downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 91 pic18f1220/1320 figure 10-12: block diagra m of rb5/pgm/kbi1 pin data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb7:rb5 and weak pull-up rd portb latch ttl input buffer st buffer rb7:rb5 in serial programming mode q3 q1 rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). rb4 pins downloaded from: http:///
pic18f1220/1320 ds30009605g-page 92 ? 2002-2015 microchip technology inc. figure 10-13: block diagram of rb6 /pgc/t1oso/t13cki/p1c/kbi2 pin data bus wr latb or wr trisb data latch tris latch rd trisb q d q ck qd en p1c data 1 0 q d q ck rd portb rb6 pin portb rd latb schmitt trigger rbpu (2) p weak pull-up q1 from other qd en set rbif rb7:rb4 pins rd portb q3 pgc from rb7 pin timer1 oscillator t1oscen t13cki note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). ttl buffer eccp1 p1c/d enable p1b/d tri-state auto-shutdown v dd downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 93 pic18f1220/1320 figure 10-14: block diagram of rb7/pgd/t1osi/p1d/kbi3 pin data bus wr latb or wr trisb data latch tris latch rd trisb q d q ck qd en p1d data 1 0 q d q ck rd portb rb7 pin portb rd latb schmitt trigger to rb6 pin rbpu (2) p weak pull-up q1 from other qd en set rbif rb7:rb4 pins rd portb q3 pgd eccp1 p1c/d enable ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). p1b/d tri-state auto-shutdown t1oscen v dd downloaded from: http:///
pic18f1220/1320 ds30009605g-page 94 ? 2002-2015 microchip technology inc. table 10-3: portb functions table 10-4: summary of register s associated with portb name bit# buffer function rb0/an4/int0 bit 0 ttl (1) /st (2) input/output port pin, analog input or external interrupt input 0. rb1/an5/tx/ck/int1 bit 1 ttl (1) /st (2) input/output port pin, analog input, enhanced usart asynchronous transmit, addressable usart synchronous clock or external interrupt input 1. rb2/p1b/int2 bit 2 ttl (1) /st (2) input/output port pin or external interrupt input 2. internal software programmable weak pull-up. rb3/ccp1/p1a bit 3 ttl (1) /st (3) input/output port pin or capture1 input/compare1 output/ pwm output. internal software programmable weak pull-up. rb4/an6/rx/dt/kbi0 bit 4 ttl (1) /st (4) input/output port pin (with interrupt-on-change), analog input, enhanced usart asynchronous receive or addressable usart synchronous data. rb5/pgm/kbi1 bit 5 ttl (1) /st (5) input/output port pin (with interrupt-on-change). internal software programmable weak pull-up. low-voltage icsp? enable pin. rb6/pgc/t1oso/t13cki/ p1c/kbi2 bit 6 ttl (1) /st (5,6) input/output port pin (with interrupt-on-change), timer1/ timer3 clock input or timer1oscillator output. internal software programmable weak pull-up. serial programming clock. rb7/pgd/t1osi/p1d/kbi3 bit 7 ttl (1) /st (5) input/output port pin (with interrupt-on-change) or timer1 oscillator input. internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a ttl input when configured as a port input pin. 2: this buffer is a schmitt trigger input when configured as the external interrupt. 3: this buffer is a schmitt trigger input when configured as the ccp1 input. 4: this buffer is a schmitt trigger input when used as eusart receive input. 5: this buffer is a schmitt trigger input when used in serial programming mode. 6: this buffer is a ttl input when used as the t13cki input. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxq qqqq uuuu uuuu latb latb data output register xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 intedg2 tmr0ip r b i p 1111 -1-1 1111 -1-1 intcon3 int2ip int1ip int2ie int1ie int2if int1if 11-0 0-00 11-0 0-00 adcon1 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 -000 0000 -000 0000 legend: x = unknown, u = unchanged, q = value depends on condition. shaded cells are not used by portb. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 95 pic18f1220/1320 11.0 timer0 module the timer0 module has the following features: software selectable as an 8-bit or 16-bit timer/ counter readable and writable dedicated 8-bit software programmable prescaler clock source selectable to be external or internal interrupt-on-overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode edge select for external clock figure 11-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register ( register 11-1 ) is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 11-1: t0con: timer0 control register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit: timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps<2:0>: timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value downloaded from: http:///
pic18f1220/1320 ds30009605g-page 96 ? 2002-2015 microchip technology inc. figure 11-1: timer0 block di agram in 8-bit mode figure 11-2: timer0 block diagram in 16-bit mode note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki maximum prescale. ra4/t0cki t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 pin note: upon reset, timer0 is enabled in 8-bit mode wit h clock input from t0cki maximum prescale. t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l ra4/t0cki pin downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 97 pic18f1220/1320 11.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 regis- ter is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the rising edge. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 11.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writable. the psa and t0ps2:t0ps0 bits determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , x , ..., etc.) will clear the prescaler count. 11.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed on-the-fly during program execution). 11.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h in 8-bit mode, or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0if bit must be cleared in soft- ware by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from low-power sleep mode, since the timer requires clock cycles even when t0cs is set. 11.4 16-bit mode timer reads and writes tmr0h is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of timer0 (refer to figure 11-2 ). the high byte of the timer0 counter/timer is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this pro- vides the ability to read all 16 bits of timer0, without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 module low byte register xxxx xxxx uuuu uuuu tmr0h timer0 module high byte register 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisa ra7 (1) ra6 (1) porta data direction register 11-1 1111 11-1 1111 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by timer0. note 1: ra6 and ra7 are enabled as i/o pins, depending on the oscillator mode selected in configuration word 1h. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 98 ? 2002-2015 microchip technology inc. 12.0 timer1 module the timer1 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr1h and tmr1l) readable and writable (both registers) internal or external clock select interrupt-on-overflow from ffffh to 0000h reset from ccp module special event trigger status of system clock operation figure 12-1 is a simplified block diagram of the timer1 module. register 12-1 details the timer1 control register. this register controls the operating mode of the timer1 module and contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). the timer1 oscillator can be used as a secondary clock source in power managed modes. when the t1run bit is set, the timer1 oscillator is providing the system clock. if the fail-safe clock monitor is enabled and the timer1 oscillator fails while providing the system clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. timer1 can also be used to provide real-time clock (rtc) functionality to applications, with only a minimal addition of external components and code overhead. register 12-1: t1con: ti mer1 control register r/w-0/0 r-1/1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 t1run: timer1 system clock status bit 1 = system clock is derived from timer1 oscillator 0 = system clock is derived from another source bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rb6/pgc/t1oso/t13cki/p1c/kbi2 (on the rising edge) 0 = internal clock (fosc/4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 99 pic18f1220/1320 12.1 timer1 operation timer1 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs = 0 , timer1 increments every instruc- tion cycle. when tmr1cs = 1 , timer1 increments on every rising edge of the external clock input, or the tim- er1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rb7/pgd/t1osi/p1d/kbi3 and rb6/t1oso/ t13cki/p1c/kbi2 pins become inputs. that is, the trisb7:trisb6 values are ignored and the pins read as 0 . timer1 also has an internal reset input. this reset can be generated by the ccp module (see section 15.4.4 ?special event trigger? ). figure 12-1: timer1 block diagram figure 12-2: timer1 block diag ram: 16-bit read/write mode tmr1h tmr1l t1sync tmr1cs t1ckps1:t1ckps0 peripheral clocks f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 10 01 synchronized clock input 2 tmr1if overflow tmr1 clr ccp special event trigger t1oscen enable oscillator (1) t1osc interrupt flag bit note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. t1osi t13cki/t1oso timer 1 tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 peripheral clocks t1oscen enable oscillator (1) tmr1if overflow interrupt f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 10 0 1 synchronized clock input 2 t13cki/t1oso t1osi tmr1 flag bit note 1: when enable bit, t1oscen, is cleared, the inverter and feedbac k resistor are turned off. this eliminates power drain. high byte data bus<7:0> 8 tmr1h 8 8 8 read tmr1l write tmr1l clr ccp special event trigger downloaded from: http:///
pic18f1220/1320 ds30009605g-page 100 ? 2002-2015 microchip technology inc. 12.2 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit, t1oscen (t1con<3>). the oscil- lator is a low-power oscillator rated for 32 khz crystals. it will continue to run during all power managed modes. the circuit for a typical lp oscillator is shown in figure 12-3 . table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 12-3: external components for the timer1 lp oscillator table 12-1: capacitor selection for the timer oscillator note: the timer1 oscillator shares the t1osi and t1oso pins with the pgd and pgc pins used for programming and debugging. when using the timer1 oscillator, in-circuit serial programming (icsp) may not function correctly (high voltage or low voltage), or the in-circuit debugger (icd) may not communicate with the controller. as a result of using either icsp or icd, the timer1 crystal may be damaged. if icsp or icd operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. the oscillator loading capacitors may remain in-circuit during icsp or icd operation. osc type freq c1 c2 lp 32 khz 22 pf (1) 22 pf (1) note 1: microchip suggests this value as a starting point in validating the oscillator circuit. oscillator operation should then be tested to ensure expected performance under all expected conditions (v dd and temperature). 2: higher capacitance increases the stabil- ity of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. note: see the notes with table 12-1 for additional information about capacitor selection. c1 c2 xtal pic18fxxxx pgd/t1osi pgc/t1oso 32.768 khz 22 pf 22 pf pgd pgc downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 101 pic18f1220/1320 12.3 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power during operation. due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 12-3 , should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor (such as the ccp1 pin in output compare or pwm mode, or the primary oscillator using the osc2 pin), a grounded guard ring around the oscillator circuit, as shown in figure 12-4 , may be helpful when used on a single sided pcb, or in addition to a ground plane. figure 12-4: oscillator circuit with grounded guard ring 12.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing timer1 interrupt enable bit, tmr1ie (pie1<0>). 12.5 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a special event trigger (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion, if the a/d mod- ule is enabled (see section 15.4.4 ?special event trigger? for more information). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer1. 12.6 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2 ). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid, due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. ra1ra4 rb0 mclr v ss ra2ra3 note: not drawn to scale. ra3 rb2 osc1 rb5 osc2 v dd rb7rb6 c2x1 c3 c4x2 c5 c1 note: the special event triggers from the ccp1 module will not set interrupt flag bit, tmr1if (pir1<0>). downloaded from: http:///
pic18f1220/1320 ds30009605g-page 102 ? 2002-2015 microchip technology inc. 12.7 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 12.2 ?timer1 oscillator? , above), gives users the option to include rtc function- ality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 12-1 , demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 reg- ister pair to overflow, triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take two seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it; the simplest method is to set the msb of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ), as shown in the routine, rtcinit . the timer1 oscillator must also be enabled and running at all times. example 12-1: implementing a real-time clock using a timer1 interrupt service rtcinit movlw 0x80 ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b00001111 ; configure for external clock, movwf t1osc ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins, f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done movlw .01 ; reset hours to 1 movwf hours return ; done downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 103 pic18f1220/1320 table 12-2: registers associated with timer1 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 u0uu uuuu legend: x = unknown, u = unchanged, C = unimplemented, read as 0 . shaded cells are not used by the timer1 module. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 104 ? 2002-2015 microchip technology inc. 13.0 timer2 module the timer2 module timer has the following features: 8-bit timer (tmr2 register) 8-bit period register (pr2) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr2 match with pr2 timer2 has a control register shown in register 13-1 . tmr2 can be shut off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. figure 13-1 is a simplified block diagram of the timer2 module. register 13-1 shows the timer2 control register. the prescaler and postscaler selection of timer2 are controlled by this register. 13.1 timer2 operation timer2 can be used as the pwm time base for the pwm mode of the ccp module. the tmr2 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, t2ckps1:t2ckps0 (t2con<1:0>). the match out- put of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit, tmr2if (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: ti mer2 control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6-3 toutps<3:0>: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 105 pic18f1220/1320 13.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 13.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module, which optionally uses it to generate the shift clock. figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 output (1) reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if toutps3:toutps0 t2ckps1:t2ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 tmr2 timer2 module register 0000 0000 0000 0000 t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, C = unimplemented, read as 0 . shaded cells are not used by the timer2 module. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 106 ? 2002-2015 microchip technology inc. 14.0 timer3 module the timer3 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers; tmr3h and tmr3l) readable and writable (both registers) internal or external clock select interrupt-on-overflow from ffffh to 0000h reset from ccp module trigger figure 14-1 is a simplified block diagram of the timer3 module. register 14-1 shows the timer3 control register. this register controls the operating mode of the timer3 module and sets the ccp clock source. register 12-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen), which can be a clock source for timer3. register 14-1: t3con: ti mer3 control register r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 rd16 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6 unimplemented : read as 0 bit 5-4 t3ckps<1:0>: timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t3ccp1: timer3 and timer1 to ccp1 enable bits 1 = timer3 is the clock source for compare/capture ccp module 0 = timer1 is the clock source for compare/capture ccp module bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the system clock comes from timer1/timer3.) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t13cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 107 pic18f1220/1320 14.1 timer3 operation timer3 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs = 0 , timer3 increments every instruc- tion cycle. when tmr3cs = 1 , timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rb7/pgd/t1osi/p1d/kbi3 and rb6/pgc/ t1oso/t13cki/p1c/kbi2 pins become inputs. that is, the trisb7:trisb6 value is ignored and the pins are read as 0 . timer3 also has an internal reset input. this reset can be generated by the ccp module (see section 15.4.4 ?special event trigger? ). figure 14-1: timer3 block diagram figure 14-2: timer3 block diagram co nfigured in 16-bit read/write mode tmr3h tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 peripheral clocks t1oscen enable oscillator (1) tmr3if overflow interrupt f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 10 01 synchronized clock input 2 t1oso/ t1osi flag bit note 1: when enable bit, t1oscen, is cleared, the inverter and feedbac k resistor are turned off. this eliminates power drain. t13cki clr ccp special event trigger t3ccpx timer3 tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 peripheral t1oscen enable oscillator (1) f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 10 01 synchronized clock input 2 t1oso/ t1osi tmr3 t13cki clr ccp special event trigger t3ccpx to timer1 clock input note 1: when the t1oscen bit is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. high byte data bus<7:0> 8 tmr3h 8 8 8 read tmr3l write tmr3l set tmr3if flag bit on overflow clocks downloaded from: http:///
pic18f1220/1320 ds30009605g-page 108 ? 2002-2015 microchip technology inc. 14.2 timer1 oscillator the timer1 oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. the oscillator is a low- power oscillator rated for 32 khz crystals. see section 12.2 ?timer1 oscillator? for further details. 14.3 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled/disabled by setting/clearing tmr3 interrupt enable bit, tmr3ie (pie2<1>). 14.4 resetting timer3 using a ccp trigger output if the ccp module is configured in compare mode to generate a special event trigger (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer3. see section 15.4.4 ?special event trigger? for more information. timer3 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer3 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer3. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccp module will not set interrupt flag bit, tmr3if (pir1<0>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 oscfif eeif lvdif tmr3if 0--0 -00- 0--0 -00- pie2 oscfie eeie lvdie tmr3ie 0--0 -00- 0--0 -00- ipr2 oscfip eeip lvdip tmr3ip 1--1 -11- 1--1 -11- tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 u0uu uuuu t3con rd16 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0-00 0000 u-uu uuuu legend: x = unknown, u = unchanged, C = unimplemented, read as 0 . shaded cells are not used by the timer3 module. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 109 pic18f1220/1320 15.0 enhanced capture/ compare/pwm (eccp) module the enhanced ccp module is implemented as a standard ccp module with enhanced pwm capabilities. these capabilities allow for two or four output channels, user-selectable polarity, dead-band control and automatic shutdown and restart and are discussed in detail in section 15.5 ?enhanced pwm mode? . the control register for ccp1 is shown in register 15-1 . in addition to the expanded functions of the ccp1con register, the eccp module has two additional registers associated with enhanced pwm operation and auto-shutdown features: pwm1con eccpas register 15-1: ccp1con register for enhanced ccp operation r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 p1m<1:0>: pwm output configuration bits if ccp1m<3:2> = 00, 01, 10 : xx = p1a assigned as capture/compare input; p1b, p1c, p1d assigned as port pins if ccp1m<3:2> = 11 : 00 = single output; p1a modulated; p1b, p1c, p1d assigned as port pins 01 = full-bridge output forward; p1d m odulated; p1a active; p1b, p1c inactive 10 = half-bridge output; p1a, p1b modulated with dead-band control; p1c, p1d assigned as port pins 11 = full-bridge output reverse; p1b modulated; p1c active; p1a, p1d inactive bit 5-4 dc1b<1:0>: pwm duty cycle least significant bits capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0 ccp1m<3:0>: eccp1 mode select bits 0000 = capture/compare/pwm off (resets eccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (eccp1if bit is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (eccp1if bit is set) 1001 = compare mode, clear output on match (eccp1if bit is set) 1010 = compare mode, generate software interrupt on match (eccp1if bit i s set, eccp1 pin returns to port pin operation) 1011 = compare mode, trigger special event (eccp1if bit is set; eccp resets tmr1 or tmr3 and starts an a/d conversion if the a/d module is enabled) 1100 = pwm mode; p1a, p1c active-high; p1b, p1d active-high 1101 = pwm mode; p1a, p1c active-high; p1b, p1d active-low 1110 = pwm mode; p1a, p1c active-low; p1b, p1d active-high 1111 = pwm mode; p1a, p1c active-low; p1b, p1d active-low downloaded from: http:///
pic18f1220/1320 ds30009605g-page 110 ? 2002-2015 microchip technology inc. 15.1 eccp outputs the enhanced ccp module may have up to four outputs, depending on the selected operating mode. these outputs, designated p1a through p1d, are multiplexed with i/o pins on portb. the pin assignments are summarized in ta b l e 1 5 - 1 . to configure i/o pins as pwm outputs, the proper pwm mode must be selected by setting the p1mn and ccp1mn bits (ccp1con<7:6> and <3:0>, respectively). the appropriate trisb direction bits for the port pins must also be set as outputs. table 15-1: pin assignments for various eccp modes 15.2 ccp module capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. table 15-2: ccp mode ? timer resource 15.3 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 or tmr3 registers when an event occurs on pin rb3/ccp1/p1a. an event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge the event is selected by control bits, ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit, ccp1if (pir1<2>), is set; it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 15.3.1 ccp pin configuration in capture mode, the rb3/ccp1/p1a pin should be configured as an input by setting the trisb<3> bit. 15.3.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (either timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchro- nous counter mode, the capture operation may not work. the timer to be used with the ccp module is selected in the t3con register. 15.3.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit, ccp1ie (pie1<2>), clear while changing capture modes to avoid false interrupts and should clear the flag bit, ccp1if, following any such change in operating mode. eccp mode ccp1con configuration rb3 rb2 rb6 rb7 compatible ccp 00xx 11xx ccp1 rb2/int2 rb6/pgc/t1oso/t13cki/kbi2 rb7/pgd/t1osi/kbi3 dual pwm 10xx 11xx p1a p1b rb6/pgc/t1oso/t13cki/kbi2 rb7/pgd/t1osi/kbi3 quad pwm x1xx 11xx p1a p1b p1c p1d legend: x = dont care. shaded cells indicate pin assignments not used by eccp in a given mode. note 1: tris register values must be configured appropriately. ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 note: if the rb3/ccp1/p1a is configured as an output, a write to the port can cause a capture condition. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 111 pic18f1220/1320 15.3.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 15-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the false interrupt. example 15-1: changing between capture prescalers figure 15-1: capture mode operat ion block diagram 15.4 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against either the tmr1 register pair value, or the tmr3 register pair value. when a match occurs, the rb3/ccp1/p1a pin: is driven high is driven low toggles output (high-to-low or low-to-high) remains unchanged (interrupt only) the action on the pin is based on the value of control bits, ccp1m3:ccp1m0. at the same time, interrupt flag bit, ccp1if, is set. 15.4.1 ccp pin configuration the user must configure the rb3/ccp1/p1a pin as an output by clearing the trisb<3> bit. 15.4.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode or synchronized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 15.4.3 software interrupt mode when generate software interrupt is chosen, the rb3/ ccp1/p1a pin is not affected. ccp1if is set and an interrupt is generated (if enabled). 15.4.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger also sets the go/done bit (adcon0<1>). this starts a conversion of the currently selected a/d channel if the a/d is on. clrf ccp1con ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode; value and ccp on movwf ccp1con ; load ccp1con with ; this value ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if tmr3 enable qs ccp1con<3:0> ccp1 pin prescaler ? 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp1 t3ccp 1 note: clearing the ccp1con register will force the rb3/ccp1/p1a compare output latch to the default low level. this is not the portb i/o data latch. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 112 ? 2002-2015 microchip technology inc. figure 15-2: compare mode operat ion block diagram table 15-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 trisb portb data direction register 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t3con rd16 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0-00 0000 u-uu uuuu adcon0 vcfg1 vcfg0 chs2 chs1 chs0 go/done adon 00-0 0000 00-0 0000 legend: x = unknown, u = unchanged, C = unimplemented, read as 0 . shaded cells are not used by capture and timer1. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if match rb3/ccp1/p1a pin trisb<3> ccp1con<3:0> mode select output enable special event trigger will: reset timer1 or timer3, but does not set timer1 or timer3 interrupt flag bit and set bit go/done (adcon0<2>), which starts an a/d conversion. tmr3h tmr3l t3ccp1 1 0 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 113 pic18f1220/1320 15.5 enhanced pwm mode the enhanced pwm mode provides additional pwm output options for a broader range of control applica- tions. the module is an upwardly compatible version of the standard ccp module and offers up to four outputs, designated p1a through p1d. users are also able to select the polarity of the signal (either active-high or active-low). the modules output mode and polarity are configured by setting the p1m1:p1m0 and ccp1m3ccp1m0 bits of the ccp1con register (ccp1con<7:6> and ccp1con<3:0>, respectively). figure 15-3 shows a simplified block diagram of pwm operation. all control registers are double-buffered and are loaded at the beginning of a new pwm cycle (the period boundary when timer2 resets) in order to prevent glitches on any of the outputs. the exception is the pwm delay register, eccp1del, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). because of the buffering, the module waits until the assigned timer resets instead of starting imme- diately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms, but are instead offset by one full instruction cycle (4 t osc ). as before, the user must manually configure the appropriate tris bits for output. 15.5.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the equation: equation 15-1: pwm period pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is copied from ccpr1l into ccpr1h 15.5.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the pwm duty cycle is calculated by the equation: equation 15-2: pwm duty cycle ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not copied into ccpr1h until a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or two bits of the tmr2 prescaler, the ccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 15-3: pwm resolution 15.5.3 pwm output configurations the p1m1:p1m0 bits in the ccp1con register allow one of four configurations: single output half-bridge output full-bridge output, forward mode full-bridge output, reverse mode the single output mode is the standard pwm mode discussed in section 15.5 ?enhanced pwm mode? . the half-bridge and full-bridge output modes are covered in detail in the sections that follow. the general relationship of the outputs in all configurations is summarized in figure 15-4 . table 15-4: example pwm frequencies and resolutions at 40 mhz note: the timer2 postscaler (see section 13.0 ?timer2 module? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] 4 t osc (tmr2 prescale value) note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value) ( ) pwm resolution (max) = f osc f pwm log log(2) bits pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz t i m e r p r e s c a l e r ( 1 , 4 , 1 6 ) 1 641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.58 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 114 ? 2002-2015 microchip technology inc. figure 15-3: simplified block diagram of the enhanced pwm module figure 15-4: pwm output relationships (active-high state) ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) rq s duty cycle registers ccp1con<5:4> clear timer, set ccp1 pin and latch d.c. note: the 8-bit tmr2 register is concatenated wit h the 2-bit internal q clock, or two bits of the prescaler to create the 10-bit time base. trisb<3> rb3/ccp1/p1a trisb<2> rb2/p1b/int2 trisb<6> rb6/pgc/t1oso/t13cki/ trisb<7> rb7/pgd/t1osi/p1d/kbi3 output controller p1m1<1:0> 2 ccp1m<3:0> 4 ccp1del ccp1/p1a p1b p1c p1d p1c/kbi2 0 period 0010 01 11 signal pr2+1 ccp1con<7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 115 pic18f1220/1320 figure 15-5: pwm output relationships (active-low state) 0 period 0010 01 11 signal pr2+1 ccp1con<7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) duty cycle = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) delay = 4 * t osc * (pwm1con<6:0>) note 1: dead-band delay is programmed using the pwm1con register ( section 15.5.6 ?programmable dead-band delay? ). downloaded from: http:///
pic18f1220/1320 ds30009605g-page 116 ? 2002-2015 microchip technology inc. 15.5.4 half-bridge mode in the half-bridge output mode, two pins are used as outputs to drive push-pull loads. the pwm output signal is output on the rb3/ccp1/p1a pin, while the complementary pwm output signal is output on the rb2/p1b/int2 pin ( figure 15-6 ). this mode can be used for half-bridge applications, as shown in figure 15-7 , or for full-bridge applications, where four power switches are being modulated with two pwm signals. in half-bridge output mode, the programmable dead- band delay can be used to prevent shoot-through current in half-bridge power devices. the value of bits, pdc6:pdc0 (pwm1con<6:0>), sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 15.5.6 ?programmable dead-band delay? for more details of the dead-band delay operations. the trisb<3> and trisb<2> bits must be cleared to configure p1a and p1b as outputs. figure 15-6: half-bridge pwm output (active-high) figure 15-7: examples of half-bri dge output mode applications period duty cycle td td (1) p1a p1b td = dead-band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. pic18f1220/1320 p1a p1b fet driver fet driver load +v - +v - fet driver fet driver v+ v- load fet driver fet driver pic18f1220/1320 p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 117 pic18f1220/1320 15.5.5 full-bridge mode in full-bridge output mode, four pins are used as outputs; however, only two outputs are active at a time. in the forward mode, pin rb3/ccp1/p1a is continu- ously active and pin rb7/pgd/t1osi/p1d/kbi3 is modulated. in the reverse mode, pin rb6/pgc/ t1oso/t13cki/p1c/kbi2 is continuously active and pin rb2/p1b/int2 is modulated. these are illustrated in figure 15-8 . the trisb<3:2> and trisb<7:6> bits must be cleared to make the p1a, p1b, p1c and p1d pins output. figure 15-8: full-bridge pwm output (active-high) period duty cycle p1ap1b p1c p1d forward mode (1) period duty cycle p1ap1c p1d p1b reverse mode (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 118 ? 2002-2015 microchip technology inc. figure 15-9: example of full-bridge application 15.5.5.1 direction change in full-bridge mode in the full-bridge output mode, the p1m1 bit in the ccp1con register allows the user to control the forward/reverse direction. when the application firmware changes this direction control bit, the module will assume the new direction on the next pwm cycle. just before the end of the current pwm period, the modulated outputs (p1b and p1d) are placed in their inactive state, while the unmodulated outputs (p1a and p1c) are switched to drive in the opposite direction. this occurs in a time interval of (4 t osc * (timer2 prescale value) before the next pwm period begins. the timer2 prescaler will be either 1,4 or 16, depend- ing on the value of the t2ckps bit (t2con<1:0>). during the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (p1b and p1d) remain inactive. this relationship is shown in figure 15-10 . note that in the full-bridge output mode, the eccp module does not provide any dead-band delay. in general, since only one output is modulated at all times, dead-band delay is not required. however, there is a situation where a dead-band delay might be required. this situation occurs when both of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. figure 15-11 shows an example where the pwm direc- tion changes from forward to reverse, at a near 100% duty cycle. at time t1, the output p1a and p1d become inactive, while output p1c becomes active. in this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices qc and qd (see figure 15-9 ) for the duration of t. the same phenom- enon will occur to power devices qa and qb for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, one of the following requirements must be met: 1. reduce pwm for a pwm period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. other options to prevent shoot-through current may exist. pic18f1220/1320 p1ap1c fet driver fet driver v+ v- load fet driver fet driver p1bp1d qaqb qd qc downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 119 pic18f1220/1320 figure 15-10: pwm direct ion change (active-high) figure 15-11: pwm direction change at near 100% duty cycle (active-high) dc pwm period (1) signal note 1: the direction bit in the ccp1 control register (ccp 1con<7>) is written any time during the pwm cycle. 2: when changing directions, the p1a and p1c toggle one timer2 count before the end of the current pwm cycle. the modulated p1b and p1d signals are inactive at this time. pwm period one timer2 count (2) p1a p1b p1c p1d dc forward period reverse period p1a t on t off t = t off C t on p1b p1cp1d external switch d potential shoot-through current note 1: t on is the turn-on delay of power switch qc and its driver. 2: t off is the turn-off delay of power switch qd and its driver. external switch c t1 dc dc downloaded from: http:///
pic18f1220/1320 ds30009605g-page 120 ? 2002-2015 microchip technology inc. 15.5.6 programmable dead-band delay in half-bridge applications where all power switches are modulated at the pwm frequency at all times, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current (shoot- through current) may flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot-through current from flow- ing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in the half-bridge output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 15-6 for an illustra- tion. the lower seven bits of the pwm1con register ( register 15-2 ) sets the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). 15.5.7 enhanced pwm auto-shutdown when the eccp is programmed for any of the enhanced pwm modes, the active output pins may be configured for auto-shutdown. auto-shutdown immedi- ately places the enhanced pwm output pins into a defined shutdown state when a shutdown event occurs. a shutdown event can be caused by the int0, int1 or int2 pins (or any combination of these three sources). the auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. the auto- shutdown sources to be used are selected using the eccpas2:eccpas0 bits (bits <6:4> of the eccpas register). when a shutdown occurs, the output pins are asynchronously placed in their shutdown states, spec- ified by the pssac1:pssac0 and pssbd1:pssbd0 bits (eccpas<3:0>). each pin pair (p1a/p1c and p1b/p1d) may be set to drive high, drive low or be tri- stated (not driving). the eccpase bit (eccpas<7>) is also set to hold the enhanced pwm outputs in their shutdown states. the eccpase bit is set by hardware when a shutdown event occurs. if automatic restarts are not enabled, the eccpase bit is cleared by firmware when the cause of the shutdown clears. if automatic restarts are enabled, the eccpase bit is automatically cleared when the cause of the auto-shutdown has cleared. if the eccpase bit is set when a pwm period begins, the pwm outputs remain in their shutdown state for that entire pwm period. when the eccpase bit is cleared, the pwm outputs will return to normal operation at the beginning of the next pwm period. note: writing to the eccpase bit is disabled while a shutdown condition is active. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 121 pic18f1220/1320 register 15-2: pwm1con: pw m configuration register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 prsen: pwm restart enable bit 1 = upon auto-shutdown, the eccpase bit clears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, eccpase must be cleared in software to restart the pwm bit 6-0 pdc<6:0>: pwm delay count bits number of f osc /4 (4 * t osc ) cycles between the scheduled time when a pwm signal should transition active and the actual time it transitions active. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 122 ? 2002-2015 microchip technology inc. register 15-3: eccpas: enhanced cap ture/compare/pwm/auto-shutdown control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 eccpase: eccp auto-shutdown event status bit 0 = eccp outputs are operating 1 = a shutdown event has occurred; eccp outputs are in shutdown state bit 6 eccpas2: eccp auto-shutdown bit 2 0 = int0 pin has no effect 1 = int0 pin low causes shutdown bit 5 eccpas1: eccp auto-shutdown bit 1 0 = int2 pin has no effect 1 = int2 pin low causes shutdown bit 4 eccpas0: eccp auto-shutdown bit 0 0 = int1 pin has no effect 1 = int1 pin low causes shutdown bit 3-2 pssacn: pins a and c shutdown state control bits 00 = drive pins a and c to 0 01 = drive pins a and c to 1 1x = pins a and c tri-state bit 1-0 pssbdn: pins b and d shutdown state control bits 00 = drive pins b and d to 0 01 = drive pins b and d to 1 1x = pins b and d tri-state downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 123 pic18f1220/1320 15.5.7.1 auto-shutdown and automatic restart the auto-shutdown feature can be configured to allow automatic restarts of the module, following a shutdown event. this is enabled by setting the prsen bit of the pwm1con register (pwm1con<7>). in shutdown mode with prsen = 1 ( figure 15-12 ), the eccpase bit will remain set for as long as the cause of the shutdown continues. when the shutdown condition clears, the eccpase bit is automatically cleared. if prsen = 0 ( figure 15-13 ), once a shutdown condition occurs, the eccpase bit will remain set until it is cleared by firmware. once eccpase is cleared, the enhanced pwm will resume at the beginning of the next pwm period. independent of the prsen bit setting, the eccpase bit cannot be cleared as long as the cause of the shutdown persists. the auto-shutdown mode can be forced by writing a 1 to the eccpase bit. 15.5.8 start-up considerations when the eccp module is used in the pwm mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the pwm output pins. when the microcontroller is released from reset, all of the i/o pins are in the high-impedance state. the external circuits must keep the power switch devices in the off state, until the microcontroller drives the i/o pins with the proper signal levels, or activates the pwm output(s). the ccp1m1:ccp1m0 bits (ccp1con<1:0>) allow the user to choose whether the pwm output signals are active-high or active-low for each pair of pwm output pins (p1a/p1c and p1b/p1d). the pwm output polarities must be selected before the pwm pins are configured as outputs. changing the polarity configura- tion while the pwm pins are configured as outputs is not recommended, since it may result in damage to the application circuits. the p1a, p1b, p1c and p1d output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pins for output at the same time as the eccp module may cause damage to the application circuit. the eccp module must be enabled in the proper output mode and complete a full pwm cycle, before con- figuring the pwm pins as outputs. the completion of a full pwm cycle is indicated by the tmr2if bit being set as the second pwm period begins. figure 15-12: pwm auto-shutdown (prsen = 1 , auto-restart enabled) figure 15-13: pwm auto-shutdown (prsen = 0 , auto-restart disabled) note: writing to the eccpase bit is disabled while a shutdown condition is active. shutdown pwm eccpase bit activity event pwm period pwm period pwm period duty cycle dead time duty cycle duty cycle dead time dead time shutdown pwm eccpase bit activity event pwm period pwm period pwm period eccpase cleared by firmware duty cycle dead time duty cycle duty cycle dead time dead time downloaded from: http:///
pic18f1220/1320 ds30009605g-page 124 ? 2002-2015 microchip technology inc. 15.5.9 setup for pwm operation the following steps should be taken when configuring the eccp1 module for pwm operation: 1. configure the pwm pins p1a and p1b (and p1c and p1d, if used) as inputs by setting the corresponding trisb bits. 2. set the pwm period by loading the pr2 register. 3. configure the eccp module for the desired pwm mode and configuration by loading the ccp1con register with the appropriate values: select one of the available output configurations and direction with the p1m1:p1m0 bits. select the polarities of the pwm output signals with the ccp1m3:ccp1m0 bits. 4. set the pwm duty cycle by loading the ccpr1l register and ccp1con<5:4> bits. 5. for half-bridge output mode, set the dead- band delay by loading pwm1con<6:0> with the appropriate value. 6. if auto-shutdown operation is required, load the eccpas register: select the auto-shutdown sources using the eccpas<2:0> bits. select the shutdown states of the pwm output pins using pssac1:pssac0 and pssbd1:pssbd0 bits. set the eccpase bit (eccpas<7>). 7. if auto-restart operation is required, set the prsen bit (pwm1con<7>). 8. configure and start tmr2: clear the tmr2 interrupt flag bit by clearing the tmr2if bit (pir1<1>). set the tmr2 prescale value by loading the t2ckps bits (t2con<1:0>). enable timer2 by setting the tmr2on bit (t2con<2>). 9. enable pwm outputs after a new pwm cycle has started: wait until tmr2 overflows (tmr2if bit is set). enable the ccp1/p1a, p1b, p1c and/or p1d pin outputs by clearing the respective trisb bits. clear the eccpase bit (eccpas<7>). 15.5.10 operation in low-power modes in the low-power sleep mode, all clock sources are disabled. timer2 will not increment and the state of the module will not change. if the eccp pin is driving a value, it will continue to drive that value. when the device wakes up, it will continue from this state. if two- speed start-ups are enabled, the initial start-up frequency may not be stable if the intosc is being used. in pri_idle mode, the primary clock will continue to clock the eccp module without change. in all other low-power modes, the selected low-power mode clock will clock timer2. other low-power mode clocks will most likely be different than the primary clock frequency. 15.5.10.1 operation with fail-safe clock monitor if the fail-safe clock monitor is enabled (config1h<6> is programmed), a clock failure will force the device into the low-power rc_run mode and the oscfif bit (pir2<7>) will be set. the eccp will then be clocked from the intrc clock source, which may have a different clock frequency than the primary clock. by loading the ircf2:ircf0 bits on resets, the user can enable the intosc at a high clock speed in the event of a clock failure. see the previous section for additional details. 15.5.11 effects of a reset both power-on and subsequent resets will force all ports to input mode and the ccp registers to their reset states. this forces the enhanced ccp module to reset to a state compatible with the standard ccp module. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 125 pic18f1220/1320 table 15-5: registers associated with enhanced pwm and timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u rcon ipen ri to pd por bor 0--1 11qq 0--q qquu pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 tmr2 timer2 module register 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 trisb portb data direction register 1111 1111 1111 1111 ccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu ccpr1l enhanced capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 eccpas eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 0000 0000 pwm1con prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 0000 0000 uuuu uuuu osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0000 qq00 0000 qq00 legend: x = unknown, u = unchanged, C = unimplemented, read as 0 . shaded cells are not used by the eccp module in enhanced pwm mode. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 126 ? 2002-2015 microchip technology inc. 16.0 enhanced addressable universal synchronous asynchronous receiver transmitter (eusart) the enhanced addressable universal synchronous asynchronous receiver transmitter (eusart) mod- ule can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers. it can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the enhanced addressable usart module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on sync break reception and 12-bit break character transmit. these features make it ideally suited for use in local interconnect network (lin) bus systems. the eusart can be configured in the following modes: asynchronous (full duplex) with: - auto-wake-up on character reception - auto-baud calibration - 12-bit break character transmission synchronous C master (half duplex) with selectable clock polarity synchronous C slave (half duplex) with selectable clock polarity the rb1/an5/tx/ck/int1 and rb4/an6/rx/dt/kbi0 pins must be configured as follows for use with the universal synchronous asynchronous receiver transmitter: spen (rcsta<7>) bit must be set ( = 1 ), pcfg6:pcfg5 (adcon1<5:6>) must be set ( = 1 ), trisb<4> bit must be set ( = 1 ) and trisb<1> bit must be set ( = 1 ). the operation of the enhanced usart module is controlled through three registers: transmit status and control (txsta) receive status and control (rcsta) baud rate control (baudctl) these are detailed in on the following pages in register 16-1 , register 16-2 and register 16-3 , respectively. 16.1 asynchronous operation in power managed modes the eusart may operate in asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. this makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the osc1 and osc2 pins. the factory calibrates the internal oscillator block out- put (intosc) for 8 mhz (see ta b l e 2 2 - 6 ). however, this frequency may drift as v dd or temperature changes and this directly affects the asynchronous baud rate. two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. the first (preferred) method uses the osctune register to adjust the intosc output back to 8 mhz. adjusting the value in the osctune register allows for fine resolution changes to the system clock source (see section 3.6 ?intosc frequency drift? for more information). the other method adjusts the value in the baud rate generator (brg). there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency. note: the eusart control will automatically reconfigure the pin from input to output as needed. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 127 pic18f1220/1320 register 16-1: txsta: transmit status and control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-1/1 r/w-0/0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 csrc: clock source select bit asynchronous mode: dont care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode: 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode: dont care. bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr idle 0 =tsr busy bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 128 ? 2002-2015 microchip technology inc. register 16-2: rcsta: receive status and control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode: dont care. synchronous mode C master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode C slave: dont care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit, cren, is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ): 1 = enables address detection, generates rcif interrupt and loads rcreg when rx9d is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ): dont care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receiving next val id byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 129 pic18f1220/1320 register 16-3: baudctl: bau d rate control register u-0 r-1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 rcidl sckp brg16 wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 rcidl : receive operation idle status bit 1 = receiver is idle 0 = receiver is busy bit 5 unimplemented: read as 0 bit 4 sckp : synchronous clock polarity select bit asynchronous mode : unused in this mode. synchronous mode : 1 = idle state for clock (ck) is a high level 0 = idle state for clock (ck) is a low level bit 3 brg16: 16-bit baud rate register enable bit 1 = 16-bit baud rate generator C spbrgh and spbrg 0 = 8-bit baud rate generator C spbrg only (compatible mode), spbrgh value ignored bit 2 unimplemented: read as 0 bit 1 wue: wake-up enable bit asynchronous mode : 1 = eusart will continue to sample the rx pin C interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = rx pin not monitored or rising edge detected synchronous mode : unused in this mode. bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = enable baud rate measurement on the next character C requires reception of a sync byte (55h); cleared in hardware upon completion 0 = baud rate measurement disabled or completed synchronous mode : unused in this mode. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 130 ? 2002-2015 microchip technology inc. 16.2 eusart baud rate generator (brg) the brg is a dedicated 8-bit or 16-bit generator, that supports both the asynchronous and synchronous modes of the eusart. by default, the brg operates in 8-bit mode; setting the brg16 bit (baudctl<3>) selects 16-bit mode. the spbrgh:spbrg register pair controls the period of a free running timer. in asynchronous mode, bits brgh (txsta<2>) and brg16 also control the baud rate. in synchronous mode, bit brgh is ignored. table 16-1 shows the formula for computation of the baud rate for different eusart modes which only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrgh:spbrg registers can be calculated using the formulas in table 16-1 . from this, the error in baud rate can be determined. an example calculation is shown in example 16-1 . typical baud rates and error values for the various asynchronous modes are shown in table 16-2 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrgh:spbrg registers causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 16.2.1 power managed mode operation the system clock is used to generate the desired baud rate; however, when a power managed mode is entered, the clock source may be operating at a differ- ent frequency than in pri_run mode. in sleep mode, no clocks are present and in pri_idle mode, the primary clock source continues to provide clocks to the baud rate generator; however, in other power managed modes, the clock frequency will probably change. this may require the value in spbrg to be adjusted. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit and make sure that the receive operation is idle before changing the system clock. 16.2.2 sampling the data on the rb4/an6/rx/dt/kbi0 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 16-1: baud rate formulas example 16-1: calculat ing baud rate error configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n + 1)] 001 8-bit/asynchronous f osc /[16 (n + 1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n + 1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = dont care, n = value of spbrgh:spbrg register pair for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: desired baud rate= f osc /(64 ([spbrgh:spbrg] + 1)) solving for spbrgh:spbrg: x = ((f osc /desired baud rate)/64) C 1 = ((16000000/9600)/64) C 1 = [25.042] = 25 calculated baud rate=16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate C desired baud rate)/desired baud rate = (9615 C 9600)/9600 = 0.16% downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 131 pic18f1220/1320 table 16-2: registers associated with baud rate generator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x baudctl rcidl sckp brg16 wue abden -1-1 0-00 -1-1 0-00 spbrgh baud rate generator register high byte 0000 0000 0000 0000 spbrg baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, C = unimplemented, read as 0 . shaded cells are not used by the brg. table 16-3: baud rates for asynchronous modes baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0 . 3 1.2 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 9.6 8.929 -6.99 6 19.2 20.833 8.51 2 57.6 62.500 8.51 0 115.2 62.500 -45.75 0 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 132 ? 2002-2015 microchip technology inc. baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 2.4 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 19.2 19.231 0.16 12 57.6 62.500 8.51 3 115.2 125.000 8.51 1 baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 19.2 19.231 0.16 12 57.6 62.500 8.51 3 115.2 125.000 8.51 1 table 16-3: baud rates for asynchronous modes (continued) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 133 pic18f1220/1320 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 115.2 111.111 -3.55 8 table 16-3: baud rates for asynchronous modes (continued) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 134 ? 2002-2015 microchip technology inc. 16.2.3 auto-baud rate detect the enhanced usart module supports the automatic detection and calibration of baud rate. this feature is active only in asynchronous mode and while the wue bit is clear. the automatic baud rate measurement sequence ( figure 16-1 ) begins whenever a start bit is received and the abden bit is set. the calculation is self-averaging. in the auto-baud rate detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx signal, the rx signal is timing the brg. in abd mode, the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream. once the abden bit is set, the state machine will clear the brg and look for a start bit. the auto-baud detect must receive a byte with the value 55h (ascii u, which is also the lin bus sync character), in order to calculate the proper bit rate. the measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming sig- nal. after a start bit, the spbrg begins counting up using the preselected clock source on the first rising edge of rx. after eight bits on the rx pin, or the fifth rising edge, an accumulated value totaling the proper brg period is left in the spbrgh:spbrg registers. once the fifth edge is seen (should correspond to the stop bit), the abden bit is automatically cleared. while calibrating the baud rate period, the brg registers are clocked at 1/8th the preconfigured clock rate. note that the brg clock will be configured by the brg16 and brgh bits. independent of the brg16 bit setting, both the spbrg and spbrgh will be used as a 16-bit counter. this allows the user to verify that no carry occurred for 8-bit modes, by checking for 00h in the spbrgh register. refer to tab l e 1 6- 4 for counter clock rates to the brg. while the abd sequence takes place, the eusart state machine is held in idle. the rcif interrupt is set once the fifth rising edge on rx is detected. the value in the rcreg needs to be read to clear the rcif interrupt. rcreg content should be discarded. 16.2.4 receiving a sync (auto-baud rate detect) to receive a sync (auto-baud rate detect): 1. configure the eusart for asynchronous receive. txen should remain clear. spbrgh:spbrg may be left as is. the controller should operate in either pri_run or pri_idle. 2. enable rxif interrupts. set rcie, peie, gie. 3. enable auto-baud rate detect. set abden. 4. when the next rcif interrupt occurs, the received baud rate has been measured. read rcreg to clear rcif and discard. check spbrgh:spbrg for a valid value. the eusart is ready for normal communications. return from the interrupt. allow the primary clock to run (pri_run or pri_idle). 5. process subsequent rcif interrupts normally as in asynchronous reception. remain in pri_run or pri_idle until communications are complete. table 16-4: brg counter clock rates note 1: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible due to bit error rates. overall system timing and communication baud rates must be taken into consideration when using the auto-baud rate detection feature. brg16 brgh brg counter clock 00 f osc /512 01 f osc /128 10 f osc /128 11 f osc /32 note: during the abd sequence, spbrg and spbrgh are both used as a 16-bit counter, independent of brg16 setting. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 135 pic18f1220/1320 figure 16-1: automatic baud rate calculation 16.3 eusart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txsta<4>). in this mode, the eusart uses standard non-return-to-zero (nrz) for- mat (one start bit, eight or nine data bits and one stop bit). the most common data format is eight bits. an on- chip dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the eusart transmits and receives the lsb first. the eusarts transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh and brg16 bits (txsta<2> and baudctl<3>). parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. asynchronous mode is available in all low-power modes; it is available in sleep mode only when auto- wake-up on sync break is enabled. when in pri_idle mode, no changes to the baud rate generator values are required; however, other low-power mode clocks may operate at another frequency than the primary clock. therefore, the baud rate generator values may need to be adjusted. when operating in asynchronous mode, the eusart module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver auto-wake-up on sync break character 12-bit break character transmit auto-baud rate detection 16.3.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 16-2 . the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit, txif (pir1<4>), is set. this interrupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit, txif, will be set, regardless of the state of enable bit, txie, and cannot be cleared in software. flag bit, txif, is not cleared immediately upon loading the transmit buffer register, txreg. txif becomes valid in the second instruction cycle following the load instruction. polling txif immediately following a load of txreg will return invalid results. while flag bit, txif, indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. status bit, trmt, is a read- only bit, which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. brg value rx pin abden bit rcif bit bit 0 bit 1 (interrupt) read rcreg brg clock start auto-cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 edge #5 001ch note 1: the abd sequence requires the eusart module to be configured in asynchronous mode and wue = 0 . spbrg xxxxh 1ch spbrgh xxxxh 00h stop bit note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit, txif, is set when enable bit, txen, is set. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 136 ? 2002-2015 microchip technology inc. to set up an asynchronous transmission: 1. initialize the spbrgh:spbrg registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 16-2: eusart transmit block diagram figure 16-3: asynchronous transmission txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rb1/an5/tx/ck/int1 pin pin buffer and control 8 ????????? spbrgh brg16 word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rb1/an5/tx/ txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy ck/int1 (pin) stop bit downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 137 pic18f1220/1320 figure 16-4: asynchronous transmiss ion (back to back) table 16-5: registers associated wi th asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg eusart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudctl rcidl sckp brg16 wue abden -1-1 0-00 -1-1 0-00 spbrgh baud rate generator register high byte 0000 0000 0000 0000 spbrg baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, C = unimplemented locations read as 0 . shaded cells are not used for asynchronous transmission. transmit shift reg. write to txreg brg output (shift clock) rb1/an5/tx/ txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy ck/int1 (pin) start bit downloaded from: http:///
pic18f1220/1320 ds30009605g-page 138 ? 2002-2015 microchip technology inc. 16.3.2 eusart asynchronous receiver the receiver block diagram is shown in figure 16-5 . the data is received on the rb4/an6/rx/dt/kbi0 pin and drives the data recovery block. the data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrgh:spbrg registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit, rcif, will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 16.3.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh:spbrg registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcif bit will be set when reception is complete. the interrupt will be acknowledged if the rcie and gie bits are set. 8. read the rcsta register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 16-5: eusart receiv e block diagram x64 baud rate clk baud rate generator rb4/an6/rx/dt/kbi0 pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 ??????? spbrg spbrgh brg16 or ? 4 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 139 pic18f1220/1320 to set up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh (see section 16.2 ?eusart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 16-6: asynchronous reception table 16-6: registers associated wi th asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x rcreg eusart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudctl rcidl sckp brg16 wue abden -1-1 0-00 -1-1 0-00 spbrgh baud rate generator register high byte 0000 0000 0000 0000 spbrg baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, C = unimplemented locations read as 0 . shaded cells are not used for asynchronous reception. start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 140 ? 2002-2015 microchip technology inc. 16.3.4 auto-wake-up on sync break character during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper byte reception cannot be per- formed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx/dt line while the eusart is operating in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit (baudctl<1>). once set, the typical receive sequence on rx/dt is disabled and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event con- sists of a high-to-low transition on the rx/dt line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) following a wake-up event, the module generates an rcif interrupt. the interrupt is generated synchro- nously to the q clocks in normal operating modes ( figure 16-7 ) and asynchronously if the device is in sleep mode ( figure 16-8 ). the interrupt condition is cleared by reading the rcreg register. the wue bit is automatically cleared once a low-to-high transition is observed on the rx line, following the wake- up event. at this point, the eusart module is in idle mode and returns to normal operation. this signals to the user that the sync break event is over. 16.3.4.1 special considerations using auto-wake-up since auto-wake-up functions by sensing rising edge transitions on rx/dt, information with any state changes before the stop bit may signal a false end-of-character and cause data or framing errors. to work properly, therefore, the initial char acter in the transmission must be all 0 s. this can be 00h (8 bytes) for standard rs-232 devices, or 000h (12 bits) for lin bus. oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs/pll mode). the sync break (or wake-up signal) character must be of sufficient length and be followed by a sufficient period, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. 16.3.4.2 special considerations using the wue bit the timing of wue and rcif events may cause some confusion when it comes to determining the validity of received data. as noted, setting the wue bit places the eusart in an idle mode. the wake-up event causes a receive interrupt by setting the rcif bit. the wue bit is cleared after this when a rising edge is seen on rx/ dt. the interrupt condition is then cleared by reading the rcreg register. ordinarily, the data in rcreg will be dummy data and should be discarded. the fact that the wue bit has been cleared (or is still set) and the rcif flag is set should not be used as an indicator of the integrity of the data in rcreg. users should consider implementing a parallel method in firmware to verify received data integrity. to assure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. figure 16-7: auto-wake-up bit (wue) timings during no rmal operation figure 16-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif cleared due to user read of rcreg note 1: the eusart remains in idle while the wue bit is set. bit set by user cleared by hardware q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif cleared due to user read of rcreg note 1: if the wake-up event requires a long oscillator warm-up time, the wue bit may be cleared wh ile the primary clock is still start ing. 2: the eusart remains in idle while the wue bit is set. sleep ends enters sleep bit set by user cleared by hardware note 1 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 141 pic18f1220/1320 16.3.5 break character sequence the enhanced usart module has the capability of sending the special break character sequences that are required by the lin bus standard. the break char- acter transmit consists of a start bit, followed by twelve 0 bits and a stop bit. the frame break character is sent whenever the sendb and txen bits (txsta<3> and txsta<5>) are set while the transmit shift register is loaded with data. note that the value of data written to txreg will be ignored and all 0 s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). note that the data value written to the txreg for the break character is ignored. the write simply serves the purpose of initiating the proper sequence. the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmis- sion. see figure 16-9 for the timing of the break character sequence. 16.3.5.1 transmitting a break signal the enhanced usart module has the capability of sending the break signal that is required by the lin bus standard. the break signal consists of a start bit, followed by twelve 0 bits and a stop bit. the break sig- nal is sent whenever the sendb (txsta<3>) and txen (txsta<5>) bits are set and txreg is loaded with data. the data written to txreg will be ignored and all 0 s will be transmitted. sendb is automatically cleared by hardware when the break signal has been sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmission. to send a break signal: 1. configure the eusart for asynchronous trans- missions (steps 1-5). initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh (see section 16.2 ?eusart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. set the sendb bit. 7. load a byte into txreg. this triggers sending a break signal. the break signal is complete when trmt is set. sendb will also be cleared. see figure 16-9 for the timing of the break signal sequence. 16.3.6 receiving a break character the enhanced usart module can receive a break character in two ways. the first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. this allows for the stop bit transition to be at the correct sampling location (12 bits for break versus start bit and eight data bits for typical data). the second method uses the auto-wake-up feature described in section 16.3.4 ?auto-wake-up on sync break character? . by enabling this feature, the eusart will sample the next two transitions on rx/dt, cause an rcif interrupt and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud rate detect feature. for both methods, the user can set the abd bit before placing the eusart in its sleep mode. 16.3.6.1 transmitting a break sync the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to set up the break character. 3. load the txreg with a dummy character to initiate transmission (the value is ignored). 4. write 55h to txreg to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware. the sync character now transmits in the preconfigured mode. when the txreg becomes empty, as indicated by the txif, the next data byte can be written to txreg. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 142 ? 2002-2015 microchip technology inc. 16.3.6.2 receiving a break sync to receive a break sync: 1. configure the eusart for asynchronous transmit and receive. txen should remain clear. spbrgh:spbrg may be left as is. 2. enable auto-wake-up. set wue. 3. enable rxif interrupts. set rcie, peie, gie. 4. the controller may be placed in any power managed mode. 5. an rcif will be generated at the beginning of the break signal. when the interrupt is received, read rcreg to clear rcif and discard. allow the controller to return to pri_run mode. 6. wait for the rx line to go high at the end of the break signal. wait for any of the following: wue to clear automatically (poll), rb4/rx to go high (poll) or for rbif to be set (poll or interrupt). if rbif is used, check to be sure that rb4/rx is high before continuing. 7. enable auto-baud rate detect. set abden. 8. return from the interrupt. allow the primary clock to start and stabilize (pri_run or pri_i- dle). 9. when the next rcif interrupt occurs, the received baud rate has been measured. read rcreg to clear rcif and discard. check spbrgh:spbrg for a valid value. the eusart is ready for normal communications. return from the interrupt. allow the primary clock to run (pri_run or pri_idle). 10. process subsequent rcif interrupts normally as in asynchronous reception. txen should now be set if transmissions are needed. txif and txie may be set if transmit interrupts are desired. remain in pri_run or pri_idle until communications are complete. clear txen and return to step 2. figure 16-9: send break character sequence write to txreg brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txif bit tx (pin) trmt bit sendb dummy write downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 143 pic18f1220/1320 16.4 eusart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txsta<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta<4>). in addition, enable bit, spen (rcsta<7>), is set in order to configure the rb1/an5/ tx/ck/int1 and rb4/an6/rx/dt/kbi0 i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor trans- mits the master clock on the ck line. clock polarity is selected with the sckp bit (baudctl<5>); setting sckp sets the idle state on ck as high, while clearing the bit sets the idle state as low. this option is provided to support microwire devices with this module. 16.4.1 eusart synchronous master transmission the eusart transmitter block diagram is shown in figure 16-2 . the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and interrupt bit, txif (pir1<4>), is set. the interrupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit, txif, will be set, regardless of the state of enable bit, txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit, txif, indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register . trmt is a read-only bit, which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrgh:spbrg registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 16-10: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rb4/an6/rx/ rb1/an5/tx/ write to txreg reg txif bit (interrupt flag) txen bit 1 1 word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg = 0 , continuous transmission of two 8-bit words. dt/kbi0 pin ck/int1 pin rb1/an5/tx/ ck/int1 pin (sckp = 0 ) (sckp = 1 ) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 144 ? 2002-2015 microchip technology inc. figure 16-11: synchronous transmis sion (through txen) table 16-7: registers associated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg eusart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudctl rcidl sckp brg16 wue abden -1-1 0-00 -1-1 0-00 spbrgh baud rate generator register high byte 0000 0000 0000 0000 spbrg baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, C = unimplemented, read as 0 . shaded cells are not used for sy nchronous master transmission. rb4/an6/rx/dt/kbi0 pin rb1/an5/tx/ck/int1 pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 145 pic18f1220/1320 16.4.2 eusart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcsta<5>), or the continuous receive enable bit, cren (rcsta<4>). data is sampled on the rb4/an6/rx/dt/kbi0 pin on the falling edge of the clock. if enable bit, sren, is set, only a single word is received. if enable bit, cren, is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrgh:spbrg registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit, rcif, will be set when reception is complete and an interrupt will be generated if the enable bit, rcie, was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 16-12: synchronous reception (master mode, sren) cren bit rb4/an6/rx/ rb1/an5/tx/ write to bit sren sren bit rcif bit (interrupt) read rxreg q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . rb1/an5/tx/ ck/int1 pin ck/int1 pin dt/kbi0 pin (sckp = 0 ) (sckp = 1 ) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 146 ? 2002-2015 microchip technology inc. table 16-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x rcreg eusart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudctl rcidl sckp brg16 wue abden -1-1 0-00 -1-1 0-00 spbrgh baud rate generator register high byte 0000 0000 0000 0000 spbrg baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, C = unimplemented, read as 0 . shaded cells are not used for synchronous master reception. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 147 pic18f1220/1320 16.5 eusart synchronous slave mode synchronous slave mode is entered by clearing bit, csrc (txsta<7>). this mode differs from the synchronous master mode in that the shift clock is supplied externally at the rb1/an5/tx/ck/int1 pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 16.5.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txreg register. c) flag bit, txif, will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit, txif, will now be set. e) if enable bit, txie, is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 16-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x txreg eusart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudctl rcidl sckp brg16 wue abden -1-1 0-00 -1-1 0-00 spbrgh baud rate generator register high byte 0000 0000 0000 0000 spbrg baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown , C = unimplemented, read as 0 . shaded cells are not used for synchronous slave transmission. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 148 ? 2002-2015 microchip technology inc. 16.5.2 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of sleep, or any idle mode and bit sren, which is a dont care in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcreg register; if the rcie enable bit is set, the inter- rupt generated will wake the chip from low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit, rcif, will be set when reception is complete. an interrupt will be generated if enable bit, rcie, was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 16-10: registers associated wi th synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 adif rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 adie rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 adip rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x rcreg eusart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudctl r c i d l s c k pb r g 1 6 wue abden -1-1 0-00 -1-1 0-00 spbrgh baud rate generator register high byte 0000 0000 0000 0000 spbrg baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, C = unimplemented, read as 0 . shaded cells are not used for synchronous slave reception. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 149 pic18f1220/1320 17.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has seven inputs for the pic18f1220/1320 devices. this module allows conversion of an analog input signal to a corresponding 10-bit digital number. a new feature for the a/d converter is the addition of programmable acquisition time. this feature allows the user to select a new channel for conversion and to set the go/done bit immediately. when the go/done bit is set, the selected channel is sampled for the pro- grammed acquisition time before a conversion is actu- ally started. this removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see register 17-3 and section 17.3 ?selecting and configuring automatic acquisition time? ). the module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 17-1 , controls the operation of the a/d module. the adcon1 register, shown in register 17-2 , configures the functions of the port pins. the adcon2 register, shown in register 17-3 , configures the a/d clock source, programmed acquisition time and justification. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 150 ? 2002-2015 microchip technology inc. register 17-1: adcon0: a/ d control register 0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 vcfg1 vcfg0 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 vcfg<1:0>: voltage reference configuration bits bit 5 unimplemented: read as 0 bit 4-2 chs<2:0>: analog channel select bits 000 = channel 0 (an0) 001 = channel 1 (an1) 010 = channel 2 (an2) 011 = channel 3 (an3) 100 = channel 4 (an4) 101 = channel 5 (an5) 110 = channel 6 (an6) 111 = unimplemented (1) bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled performing a conversion on unimplemented channels returns full-scale results. note 1: performing a conversion on unimplemented channels returns full-scale results. a/d v ref +a / d v ref - 00 av dd av ss 01 external v ref +a v ss 10 av dd external v ref - 11 external v ref + external v ref - downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 151 pic18f1220/1320 register 17-2: adcon1: a/ d control register 1 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 pcfg6: a/d port configuration bit C an6 1 = pin configured as a digital port 0 = pin configured as an analog channel C digital input disabled and reads 0 bit 5 pcfg5: a/d port configuration bit C an5 1 = pin configured as a digital port 0 = pin configured as an analog channel C digital input disabled and reads 0 bit 4 pcfg4: a/d port configuration bit C an4 1 = pin configured as a digital port 0 = pin configured as an analog channel C digital input disabled and reads 0 bit 3 pcfg3: a/d port configuration bit C an3 1 = pin configured as a digital port 0 = pin configured as an analog channel C digital input disabled and reads 0 bit 2 pcfg2: a/d port configuration bit C an2 1 = pin configured as a digital port 0 = pin configured as an analog channel C digital input disabled and reads 0 bit 1 pcfg1: a/d port configuration bit C an1 1 = pin configured as a digital port 0 = pin configured as an analog channel C digital input disabled and reads 0 bit 0 pcfg0: a/d port configuration bit C an0 1 = pin configured as a digital port 0 = pin configured as an analog channel C digital input disabled and reads 0 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 152 ? 2002-2015 microchip technology inc. register 17-3: adcon2: a/ d control register 2 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as 0 bit 5-3 acqt<2:0>: a/d acquisition time select bits 000 = 0 t ad (1) 001 = 2 t ad 010 = 4 t ad 011 = 6 t ad 100 = 8 t ad 101 = 12 t ad 110 = 16 t ad 111 = 20 t ad ) bit 2-0 adcs<2:0>: a/d conversion clock select bits 000 = f osc /2 001 = f osc /8 010 = f osc /32 011 = f rc (clock derived from a/d rc oscillator) (1) 100 = f osc /4 101 = f osc /16 110 = f osc /64 111 = f rc (clock derived from a/d rc oscillator) (1) note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 153 pic18f1220/1320 the analog reference voltage is software selectable to either the devices positive and negative supply voltage (av dd and av ss ), or the voltage level on the ra3/an3/ v ref + and ra2/an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input, or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0 register) is cleared and a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 17-1 . figure 17-1: a/d block diagram (input voltage) v ain v refh reference voltage av dd vcfg1:vcfg0 chs2:chs0 an6 (1) an5an4 an3/v ref + an2/v ref - an1an0 111110 101 100 011 010 001 000 10-bit converter v refl av ss a/d note 1: i/o pins have diode protection to v dd and v ss . 0x 1x x1 x0 av dd downloaded from: http:///
pic18f1220/1320 ds30009605g-page 154 ? 2002-2015 microchip technology inc. the value in the adresh/adresl registers is not modified for a power-on reset. the adresh/adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 17.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d acquisition time (adcon2) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time (if required). 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit, adif, if required. 7. for the next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 17-2: analog input model v ain c pin rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic ?? 1k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v4v 3v 2v 567891011 (k ? ) v dd 500 na legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance ss = sampling switch c hold = sample/hold capacitance (from dac) r ss = sampling switch resistance downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 155 pic18f1220/1320 17.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 17-2 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k ? . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 17-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 17-1 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: c hold = 120 pf rs = 2.5 k ?? conversion error ? 1/2 lsb v dd =5v ? r ss = 7 k ? temperature = 50 ? c (system max.) v hold = 0v @ time = 0 17.2 a/d v ref + and v ref - references if external voltage references are used instead of the internal av dd and av ss sources, the source imped- ance of the v ref + and v ref - voltage sources must be considered. during acquisition, currents supplied by these sources are insignificant. however, during conversion, the a/d module sinks and sources current through the reference sources. in order to maintain the a/d accuracy, the voltage reference source impedances should be kept low to reduce voltage changes. these voltage changes occur as reference currents flow through the reference source impedance. the maximum recommended impedance of the v ref + and v ref - external reference voltage sources is 250 ? . equation 17-1: acquisition time equation 17-2: a/d minimum charging time example 17-1: calculating the minimu m required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperat ure coefficient =t amp + t c + t coff v hold = ( ? v ref C ( ? v ref /2048)) (1 C e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =5 ? s t coff =(temp C 25oc)(0.05 ? s/oc) (50oc C 25oc)(0.05 ? s/oc) 1.25 ? s temperature coefficient is only required for temperatures > 25oc. below 25oc, t coff = 0 ? s. t c = -(c hold )(r ic + r ss + r s ) ln(1/2047) ? s -(120 pf) (1 k ? + 7 k ? + 2.5 k ? ) ln(0.0004883) ? s 9.61 ? s t acq =5 ? s + 1.25 ? s + 9.61 ? s 12.86 ? s downloaded from: http:///
pic18f1220/1320 ds30009605g-page 156 ? 2002-2015 microchip technology inc. 17.3 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt2:acqt0 bits (adcon2<5:3>) remain in their reset state ( 000 ) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a programmable acquisition time for the a/d module. when the go/done bit is set, the a/d module contin- ues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/ d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 17.4 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible, but greater than the minimum t ad (approximately 2 ? s, see parameter 130 for more information). table 17-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 17-1: t ad vs. device operating frequencies ad clock source (t ad ) maximum device frequency operation adcs2:adcs0 pic18f1220/1320 pic18lf1220/1320 (4) 2 t osc 000 1.25 mhz 666 khz 4 t osc 100 2.50 mhz 1.33 mhz 8 t osc 001 5.00 mhz 2.66 mhz 16 t osc 101 10.0 mhz 5.33 mhz 32 t osc 010 20.0 mhz 10.65 mhz 64 t osc 110 40.0 mhz 21.33 mhz rc (3) x11 1.00 mhz (1) 1.00 mhz (2) note 1: the rc source has a typical t ad time of 4 ? s. 2: the rc source has a typical t ad time of 6 ? s. 3: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or the a/d accuracy may be out of specification. 4: low-power devices only. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 157 pic18f1220/1320 17.5 operation in low-power modes the selection of the automatic acquisition time and the a/d conversion clock is determined, in part, by the low- power mode clock source and frequency while in a low-power mode. if the a/d is expected to operate while the device is in a low-power mode, the acqt2:acqt0 and adcs2:adcs0 bits in adcon2 should be updated in accordance with the low-power mode clock that will be used. after the low-power mode is entered (either of the run modes), an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same low-power mode clock source until the conver- sion has been completed. if desired, the device may be placed into the corresponding low-power (any)_idle mode during the conversion. if the low-power mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in the low-power sleep mode requires the a/ d rc clock to be selected. if bits, acqt2:acqt0, are set to 000 and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to low-power sleep mode. the idlen and scs bits in the osccon register must have already been cleared prior to starting the conversion. 17.6 configuring analog port pins the adcon1, trisa and trisb registers all configure the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins con- figured as digital inputs will convert an analog input. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the devices specification limits. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 158 ? 2002-2015 microchip technology inc. 17.7 a/d conversions figure 17-3 shows the operation of the a/d converter after the go bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the follow- ing instruction to allow entry into low-power sleep mode before the conversion begins. figure 17-4 shows the operation of the a/d converter after the go bit has been set and the acqt2:acqt0 bits are set to 010 and selecting a 4 t ad acquisition time before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/ d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. figure 17-3: a/d conversion t ad cycles (a cqt <2:0> = 000 , t acq = 0 ) figure 17-4: a/d conversion t ad cycles (a cqt <2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy C t ad next q4: adresh/adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 1 2 3 4 5 6 7 8 11 set go bit (holding capacitor is disconnected) 9 10 next q4: adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 159 pic18f1220/1320 17.8 use of the ccp1 trigger an a/d conversion can be started by the special event trigger of the ccp1 module. this requires that the ccp1m3:ccp1m0 bits (ccp1con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/ done bit will be set, starting the a/d acquisition and conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to auto- matically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module, but will still reset the timer1 (or timer3) counter. table 17-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 0000 0000 0000 pir1 a d i f rcif txif ccp1if tmr2if tmr1if -000 -000 -000 -000 pie1 a d i e rcie txie ccp1ie tmr2ie tmr1ie -000 -000 -000 -000 ipr1 a d i p rcip txip ccp1ip tmr2ip tmr1ip -111 -111 -111 -111 pir2 oscfif eeif lvdif tmr3if 0--0 -00- 0--0 -00- pie2 oscfie eeie lvdie tmr3ie 0--0 -00- 0--0 -00- ipr2 oscfip eeip lvdip tmr3ip 1--1 -11- 1--1 -11- adresh a/d result register high byte xxxx xxxx uuuu uuuu adresl a/d result register low byte xxxx xxxx uuuu uuuu adcon0 vcfg1 vcfg0 chs2 chs1 chs0 go/done adon 00-0 0000 00-0 0000 adcon1 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 -000 0000 -000 0000 adcon2 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 0-00 0000 porta ra7 (3) ra6 (2) ra5 (1) ra4 ra3 ra2 ra1 ra0 qq0x 0000 uu0u 0000 trisa trisa7 (3) trisa6 (2) porta data direction register qq-1 1111 11-1 1111 portb read portb pins, write latb latch xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 latb portb output data latch xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, q = depends on config1h<3:0>, C = unimplemented, read as 0 . shaded cells are not used for a/d conversion. note 1: ra5 port bit is available only as an input pin when t he mclre bit in the configuration register is 0 . 2: ra6 and trisa6 are available only when the primary oscillator mode selection offe rs ra6 as a port pin; otherwise, ra6 always reads 0 , trisa6 always reads 1 and writes to both are ignored (see config1h<3:0>). 3: ra7 and trisa7 are available only when the internal rc osc illator is configured as the primary oscillator in con- fig1h<3:0>; otherwise, ra7 always reads 0 , trisa7 always reads 1 and writes to both are ignored. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 160 ? 2002-2015 microchip technology inc. 18.0 low-voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do housekeeping tasks, before the device voltage exits the valid operating range. this can be done using the low-voltage detect module. this module is a software programmable circuitry, where a device voltage trip point can be specified. when the voltage of the device becomes lower then the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to that interrupt source. the low-voltage detect circuitry is completely under software control. this allows the circuitry to be turned off by the software, which minimizes the current consumption for the device. figure 18-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . the difference, t b C t a , is the total time for shutdown. the block diagram for the lvd module is shown in figure 18-2 (following page). a comparator uses an internally generated reference voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit is set. each node in the resistor divider represents a trip point voltage. the trip point voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2v internal reference voltage generated by the voltage reference module. the comparator then generates an interrupt signal setting the lvdif bit. this voltage is software programmable to any one of 16 values (see figure 18-2 ). the trip point is selected by programming the lvdl3:lvdl0 bits (lvdcon<3:0>). figure 18-1: typical lo w-voltage detect application time voltage v a v b t a t b legend: v a = lvd trip point v b = minimum valid device operating voltage downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 161 pic18f1220/1320 figure 18-2: low-voltage detect (lvd) block diagram the lvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when bits, lvdl3:lvdl0, are set to 1111 . in this state, the com- parator input is multiplexed from the external input pin, lvdin (figure 18-3). this gives users flexibility, because it allows them to configure the low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 18-3: low-voltage detect (lvd ) with external input block diagram lvdif v dd 16-to-1 mux lvden lvd control register internally generated reference voltage lvdin 1.2v lvd en lvd control 16-to-1 mux bgap boden lvden vxen lvdin register v dd v dd externally generated trip point downloaded from: http:///
pic18f1220/1320 ds30009605g-page 162 ? 2002-2015 microchip technology inc. 18.1 control register the low-voltage detect control register controls the operation of the low-voltage detect circuitry. register 18-1: lvdcon: low-volt age detect control register u-0 u-0 r-0/0 r/w-0/0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low-voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low-voltage detect logic will not generate the interrupt flag at the specified volt- age range and the lvd interrupt should not be enabled bit 4 lvden: low-voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl<3:0>: low-voltage detection limit bits (1) 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.04v-5.15v 1101 = 3.76v-4.79v 1100 = 3.58v-4.56v 1011 = 3.41v-4.34v 1010 = 3.23v-4.11v 1001 = 3.14v-4.00v 1000 = 2.96v-3.77v 0111 = 2.70v-3.43v 0110 = 2.53v-3.21v 0101 = 2.43v-3.10v 0100 = 2.25v-2.86v 0011 = 2.16v-2.75v 0010 = 1.99v-2.53v 0001 = reserved 0000 = reserved note 1: lvdl<3:0> modes, which result in a trip point below the valid operating voltage of the device, are not tested. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 163 pic18f1220/1320 18.2 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be constantly operating. to decrease the current require- ments, the lvd circuitry only needs to be enabled for short periods, where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to set up the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvdcon register), which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set, until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 18-4 shows typical waveforms that the lvd module may be used to detect. figure 18-4: low-voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated t ivrst lvdif may not be set. enable lvd lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable t ivrst downloaded from: http:///
pic18f1220/1320 ds30009605g-page 164 ? 2002-2015 microchip technology inc. 18.2.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter 36. the low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 18-4 . 18.2.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter d022b. 18.3 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 18.4 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 165 pic18f1220/1320 19.0 special features of the cpu pic18f1220/1320 devices include several features intended to maximize system reliability, minimize cost through elimination of external components and offer code protection. these are: oscillator selection resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) fail-safe clock monitor two-speed start-up code protection id locations in-circuit serial programming several oscillator options are available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. these are discussed in detail in section 2.0 ?oscillator configurations? . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up timers provided for resets, pic18f1220/1320 devices have a watchdog timer, which is either permanently enabled via the configuration bits, or software controlled (if configured as disabled). the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two- speed start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 19.1 configuration bits the configuration bits can be programmed (read as 0 ), or left unprogrammed (read as 1 ), to select vari- ous device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h-3fffffh), which can only be accessed using table reads and table writes. programming the configuration registers is done in a manner similar to programming the flash memory. the eecon1 register wr bit starts a self-timed write to the configuration register. in normal operation mode, a tblwt instruction, with the tblptr pointing to the configuration register, sets up the address and the data for the configuration register write. setting the wr bit starts a long write to the configuration register. the configuration registers are written a byte at a time. to write or erase a configuration cell, a tblwt instruction can write a 1 or a 0 into the cell. for additional details on flash programming, refer to section 6.5 ?writing to flash program memory? . table 19-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ieso fscm fosc3 fosc2 fosc1 fosc0 11-- 1111 300002h config2l borv1 borv0 bor pwrten ---- 1111 300003h config2h wdtps3 wdtps2 wdtps1 wdtps0 wdt ---1 1111 300005h config3h mclre 1--- ---- 300006h config4l debug l v p s t v r 1--- -1-1 300008h config5l c p 1c p 0 ---- --11 300009h config5h cpd cpb 11-- ---- 30000ah config6l w r t 1w r t 0 ---- --11 30000bh config6h wrtd wrtb wrtc 111- ---- 30000ch config7l ebtr1 ebtr0 ---- --11 30000dh config7h e b t r b -1-- ---- 3ffffeh devid1 (1) dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (1) 3fffffh devid2 (1) dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 0111 legend: x = unknown, u = unchanged, C = unimplemented. shaded cells are unimplemented, read as 0 . note 1: see register 19-12 for devid1 values. devid registers are read-only and cannot be programmed by the user. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 166 ? 2002-2015 microchip technology inc. register 19-1: config1h: configuration register 1 high (byte address 300001h) r/p-1 r/p-1 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ieso fscm fosc3 fosc2 fosc1 fosc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7 ieso: internal external switchover bit 1 = internal external switchover mode enabled 0 = internal external switchover mode disabled bit 6 fscm: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled bit 5-4 unimplemented: read as 0 bit 3-0 fosc<3:0>: oscillator selection bits 11xx = external rc oscillator, clko function on ra6 1001 = internal rc oscillator, clko function on ra6 and port function on ra7 1000 = internal rc oscillator, port function on ra6 and port function on ra7 0111 = external rc oscillator, port function on ra6 0110 = hs oscillator, pll enabled (clock frequency = 4 x fosc1) 0101 = ec oscillator, port function on ra6 0100 = ec oscillator, clko function on ra6 0010 = hs oscillator 0001 = xt oscillator 0000 = lp oscillator downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 167 pic18f1220/1320 register 19-2: config2l: configuration register 2 low (byte address 300002h) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 borv1 borv0 bor (1) pwrten (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7-4 unimplemented: read as 0 bit 3-2 borv<1:0>: brown-out reset voltage bits 11 = reserved 10 = v bor set to 2.7v 01 = v bor set to 4.2v 00 = v bor set to 4.5v bit 1 bor: brown-out reset enable bit (1) 1 = brown-out reset enabled 0 = brown-out reset disabled bit 0 pwrten : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled note 1: the power-up timer is decoupled from brown-out reset, allowing these features to be independently controlled. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 168 ? 2002-2015 microchip technology inc. register 19-3: config2h: configuration register 2 high (byte address 300003h) u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 wdtps3 wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7-5 unimplemented: read as 0 bit 4-1 wdtps<3:0>: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 wdt: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 169 pic18f1220/1320 register 19-4: config3h: configuration register 3 high (byte address 300005h) r/p-1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 mclre bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7 mclre: mclr pin enable bit 1 =mclr pin enabled, ra5 input pin disabled 0 = ra5 input pin enabled, mclr disabled bit 6-0 unimplemented: read as 0 register 19-5: config4l: configuration register 4 low (byte address 300006h) r/p-1 u-0 u-0 u-0 u-0 r/p-1 u-0 r/p-1 debug l v p s t v r bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7 debug : background debugger enable bit (see note) 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug bit 6-3 unimplemented: read as 0 bit 2 lvp: low-voltage icsp enable bit 1 = low-voltage icsp enabled 0 = low-voltage icsp disabled bit 1 unimplemented: read as 0 bit 0 stvr: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset note: the timer1 oscillator shares the t1osi and t1oso pins with the pgd and pgc pins used for programming and debugging. when using the timer1 oscillator, in-circuit serial programming (icsp) may not function correctly (high voltage or low voltage), or the in-circuit debugger (icd) may not communicate with the controller. as a result of using either icsp or icd, the timer1 crystal may be damaged. if icsp or icd operations are required, the crystal should be disconnected from the circuit (disconnect either lead) or installed after programming. the oscillator loading capacitors may remain in-circuit during icsp or icd operation. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 170 ? 2002-2015 microchip technology inc. register 19-6: config5l: configuration re gister 5 low (byte address 300008h) u-0 u-0 u-0 u-0 u-0 u-0 r/c-1 r/c-1 c p 1c p 0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared c = clearable bit bit 7-2 unimplemented: read as 0 bit 1 cp1: code protection bit (pic18f1320) 1 = block 1 (001000-001fffh) not code-protected 0 = block 1 (001000-001fffh) code-protected bit 0 cp0: code protection bit (pic18f1320) 1 = block 0 (00200-000fffh) not code-protected 0 = block 0 (00200-000fffh) code-protected bit 1 cp1: code protection bit (pic18f1220) 1 = block 1 (000800-000fffh) not code-protected 0 = block 1 (000800-000fffh) code-protected bit 0 cp0: code protection bit (pic18f1220) 1 = block 0 (000200-0007ffh) not code-protected 0 = block 0 (000200-0007ffh) code-protected register 19-7: config5h: configuration register 5 high (byte address 300009h) r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 cpd cpb bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared c = clearable bit bit 7 cpd: data eeprom code protection bit 1 = data eeprom not code-protected 0 = data eeprom code-protected bit 6 cpb: boot block code protection bit 1 = boot block (000000-0001ffh) not code-protected 0 = boot block (000000-0001ffh) code-protected bit 5-0 unimplemented: read as 0 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 171 pic18f1220/1320 register 19-8: config6l: configuration register 6 low (byte address 30000ah) u-0 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 wrt1 wrt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7-2 unimplemented: read as 0 bit 1 wrt1: write protection bit (pic18f1320) 1 = block 1 (001000-001fffh) not write-protected 0 = block 1 (001000-001fffh) write-protected bit 0 wrt0: write protection bit (pic18f1320) 1 = block 0 (00200-000fffh) not write-protected 0 = block 0 (00200-000fffh) write-protected bit 1 wrt1: write protection bit (pic18f1220) 1 = block 1 (000800-000fffh) not write-protected 0 = block 1 (000800-000fffh) write-protected bit 0 wrt0: write protection bit (pic18f1220) 1 = block 0 (000200-0007ffh) not write-protected 0 = block 0 (000200-0007ffh) write-protected register 19-9: config6h: configuration register 6 high (byte address 30000bh) r/p-1 r/p-1 r-1 u-0 u-0 u-0 u-0 u-0 wrtd wrtb wrtc (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7 wrtd: data eeprom write protection bit 1 = data eeprom not write-protected 0 = data eeprom write-protected bit 6 wrtb: boot block write protection bit 1 = boot block (000000-0001ffh) not write-protected 0 = boot block (000000-0001ffh) write-protected bit 5 wrtc: configuration register write protection bit (1) 1 = configuration registers (300000-3000ffh) not write-protected 0 = configuration registers (300000-3000ffh) write-protected bit 4-0 unimplemented: read as 0 note 1: this bit is read-only in normal execution mode; it can be written only in program mode. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 172 ? 2002-2015 microchip technology inc. register 19-10: config7l: configuration register 7 low (byte address 30000ch) u-0 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 ebtr1 ebtr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7-2 unimplemented: read as 0 bit 1 ebtr1: table read protection bit (pic18f1320) 1 = block 1 (001000-001fffh) not protected from table reads executed in other blocks 0 = block 1 (001000-001fffh) protected from table reads executed in other blocks bit 0 ebtr0: table read protection bit (pic18f1320) 1 = block 0 (00200-000fffh) not protected from table reads executed in other blocks 0 = block 0 (00200-000fffh) protected from table reads executed in other blocks bit 1 ebtr1: table read protection bit (pic18f1220) 1 = block 1 (000800-000fffh) not protected from table reads executed in other blocks 0 = block 1 (000800-000fffh) protected from table reads executed in other blocks bit 0 ebtr0: table read protection bit (pic18f1220) 1 = block 0 (000200-0007ffh) not protected from table reads executed in other blocks 0 = block 0 (000200-0007ffh) protected from table reads executed in other blocks register 19-11: config7h: configuration register 7 high (byte address 30000dh) u-0 r/p-1 u-0 u-0 u-0 u-0 u-0 u-0 ebtrb bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared p = programmable bit bit 7 unimplemented: read as 0 bit 6 ebtrb: boot block table read protection bit 1 = boot block (000000-0001ffh) not protected from table reads executed in other blocks 0 = boot block (000000-0001ffh) protected from table reads executed in other blocks bit 5-0 unimplemented: read as 0 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 173 pic18f1220/1320 register 19-12: devid1: device id register 1 for pic18f1220/1320 devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-5 dev<2:0>: device id bits 111 = pic18f1220 110 = pic18f1320 bit 4-0 rev<4:0>: revision id bits these bits are used to indicate the device revision. register 19-13: devid2: device id register 2 for pic18f1220/1320 devices rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 dev<10:3>: device id bits these bits are used with the dev<2:0> bits in the device id register 1 to identify the part number. 0000 0111 = pic18f1220/1320 devices note 1: these values for dev<10:3> may be shared with other devices. the specific device is always identified by using the entire dev<10:0> bit sequence. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 174 ? 2002-2015 microchip technology inc. 19.2 watchdog timer (wdt) for pic18f1220/1320 devices, the wdt is driven by the intrc source. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexer, controlled by bits in configuration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and posts- caler are cleared when any of the following events occur: execute a sleep or clrwdt instruction, the ircf bits (osccon<6:4>) are changed or a clock failure has occurred. adjustments to the internal oscillator clock period using the osctune register also affect the period of the wdt by the same factor. for example, if the intrc period is increased by 3%, then the wdt period is increased by 3%. 19.2.1 control register register 19-14 shows the wdtcon register. this is a readable and writable register, which contains a control bit that allows software to override the wdt enable configuration bit, only if the configuration bit has disabled the wdt. figure 19-1: wdt block diagram note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: changing the setting of the ircf bits (osccon<6:4>) clears the wdt and postscaler counts. 3: when a clrwdt instruction is executed the postscaler count will be cleared. register 19-14: wdtcon: wat chdog timer control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 s w d t e n (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-1 unimplemented: read as 0 bit 0 swdten: software controlled watchdog timer enable bit (1) 1 = watchdog timer is on 0 = watchdog timer is off note 1: this bit has no effect if the configuration bit, wdten (config2h<0>), is enabled. intrc oscillator wdt wake-up reset wdt wdt counter (31 khz) programmable postscaler 1:1 to 1:32,768 enable wdt wdtps<3:0> swdten wdten clrwdt 4 from sleep reset all device sleep intrc control reset s ? 125 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 175 pic18f1220/1320 table 19-2: summary of watchdog timer registers 19.3 two-speed start-up the two-speed start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the intrc oscil- lator as a clock source until the primary clock source is available. it is enabled by setting the ieso bit in configuration register 1h (config1h<7>). two-speed start-up is available only if the primary oscil- lator mode is lp, xt, hs or hspll (crystal-based modes). other sources do not require an ost start-up delay; for these, two-speed start-up is disabled. when enabled, resets and wake-ups from sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the power-up timer after a power-on reset is enabled. this allows almost immediate code execution while the primary oscillator starts and the ost is running. once the ost times out, the device automatically switches to pri_run mode. because the osccon register is cleared on reset events, the intosc (or postscaler) clock source is not initially available after a reset event; the intrc clock is used directly at its base frequency. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits, ifrc2:ifrc0, immediately after reset. for wake-ups from sleep, the intosc or post- scaler clock sources can be selected by setting ifrc2:ifrc0 prior to entering sleep mode. in all other power managed modes, two-speed start-up is not used. the device will be clocked by the currently selected clock source until the primary clock source becomes available. the setting of the ieso bit is ignored. 19.3.1 special considerations for using two-speed start-up while using the intrc oscillator in two-speed start- up, the device still obeys the normal command sequences for entering power managed modes, includ- ing serial sleep instructions (refer to section 3.1.3 ?multiple sleep commands? ). in practice, this means that user code can change the scs1:scs0 bit settings and issue sleep commands before the ost times out. this would allow an application to briefly wake-up, per- form routine housekeeping tasks and return to sleep before the device starts to operate from the primary oscillator. user code can also check if the primary clock source is currently providing the system clocking by checking the status of the osts bit (osccon<3>). if the bit is set, the primary oscillator is providing the system clock. otherwise, the internal oscillator block is providing the clock during wake-up from reset or sleep mode. figure 19-2: timing transition for tw o-speed start-up (intosc to hspll) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h wdtps3 wdtps2 wdtps2 wdtps0 wdten rcon ipen ri to pd por bor wdtcon s w d t e n legend: shaded cells are not used by the watchdog timer. q1 q3 q4 osc1 peripheral program pc pc + 2 intosc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 q4 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t pll (1) 12345678 clock transition osts bit set multiplexer t ost (1) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 176 ? 2002-2015 microchip technology inc. 19.4 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the micro- controller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. the fscm function is enabled by setting the fail-safe clock monitor enable bit, fscm (config1h<6>). when fscm is enabled, the intrc oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. clock monitoring (shown in figure 19-3 ) is accom- plished by creating a sample clock signal, which is the intrc output divided by 64. this allows ample time between fscm sample clocks for a peripheral clock edge to occur. the peripheral system clock and the sample clock are presented as inputs to the clock monitor latch (cm). the cm is set on the falling edge of the system clock source, but cleared on the rising edge of the sample clock. figure 19-3: fscm block diagram clock failure is tested for on the falling edge of the sam- ple clock. if a sample clock falling edge occurs while cm is still set, a clock failure has been detected ( figure 19-4 ). this causes the following: the fscm generates an oscillator fail interrupt by setting bit, oscfif (pir2<7>); the system clock source is switched to the internal oscillator block (osccon is not updated to show the current clock source C this is the fail-safe condition); and the wdt is reset. since the postscaler frequency from the internal oscil- lator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate power managed mode (see section 19.3.1 ?special considerations for using two-speed start-up? and section 3.1.3 ?multiple sleep commands? for more details). this can be done to attempt a partial recovery, or execute a controlled shutdown. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits, ifrc2:ifrc0, immediately after reset. for wake-ups from sleep, the intosc or postscaler clock sources can be selected by setting ifrc2:ifrc0 prior to entering sleep mode. adjustments to the internal oscillator block, using the osctune register, also affect the period of the fscm by the same factor. this can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. the fscm will detect failures of the primary or second- ary clock sources only. if the internal oscillator block fails, no failure would be detected, nor would any action be possible. 19.4.1 fscm and the watchdog timer both the fscm and the wdt are clocked by the intrc oscillator. since the wdt operates with a separate divider and counter, disabling the wdt has no effect on the operation of the intrc oscillator when the fscm is enabled. as already noted, the clock source is switched to the intosc clock when a clock failure is detected. depending on the frequency selected by the ircf2:ircf0 bits, this may mean a substantial change in the speed of code execution. if the wdt is enabled with a small prescale value, a decrease in clock speed allows a wdt time-out to occur and a subsequent device reset. for this reason, fail-safe clock events also reset the wdt and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. peripheral intrc 64 s c q (32 ? s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected source clock q downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 177 pic18f1220/1320 19.4.2 exiting fail-safe operation the fail-safe condition is terminated by either a device reset, or by entering a power managed mode. on reset, the controller starts the primary clock source specified in configuration register 1h (with any required start-up delays that are required for the oscillator mode, such as ost or pll timer). the intosc multiplexer provides the system clock until the primary clock source becomes ready (similar to a two- speed start-up). the clock system source is then switched to the primary clock (indicated by the osts bit in the osccon register becoming set). the fail- safe clock monitor then resumes monitoring the peripheral clock. the primary clock source may never become ready during start-up. in this case, operation is clocked by the intosc multiplexer. the osccon register will remain in its reset state until a power managed mode is entered. entering a power managed mode by loading the osccon register and executing a sleep instruction will clear the fail-safe condition. when the fail-safe condition is cleared, the clock monitor will resume monitoring the peripheral clock. 19.4.3 fscm interrupts in power managed modes as previously mentioned, entering a power managed mode clears the fail-safe condition. by entering a power managed mode, the clock multiplexer selects the clock source selected by the osccon register. fail-safe monitoring of the power managed clock source resumes in the power managed mode. if an oscillator failure occurs during power managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. if enabled (oscfif = 1 ), code execution will be clocked by the intosc multiplexer. an automatic transition back to the failed clock source will not occur. if the interrupt is disabled, the device will not exit the power managed mode on oscillator failure. instead, the device will continue to operate as before, but clocked by the intosc multiplexer. while in idle mode, subse- quent interrupts will cause the cpu to begin executing instructions while being clocked by the intosc multi- plexer. the device will not transition to a different clock source until the fail-safe condition is cleared. figure 19-4: fscm timing diagram oscfif cm output system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test downloaded from: http:///
pic18f1220/1320 ds30009605g-page 178 ? 2002-2015 microchip technology inc. 19.4.4 por or wake from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary system clock is ec, rc or intrc modes, monitoring can begin immediately following these events. for oscillator modes involving a crystal or resonator (hs, hspll, lp or xt), the situation is somewhat dif- ferent. since the oscillator may require a start-up time considerably longer than the fcsm sample clock time, a false clock failure may be detected. to prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source as noted in section 19.3.1 ?special considerations for using two-speed start-up? , it is also possible to select another clock configuration and enter an alter- nate power managed mode while waiting for the primary system clock to become stable. when the new powered managed mode is selected, the primary clock is disabled. note: the same logic that prevents false oscilla- tor failure interrupts on por or wake from sleep will also prevent the detection of the oscillators failure to start at all following these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 179 pic18f1220/1320 19.5 program verification and code protection the overall structure of the code protection on the pic18 flash devices differs significantly from other pic devices. the user program memory is divided into three blocks. one of these is a boot block of 512 bytes. the remain- der of the memory is divided into two blocks on binary boundaries. each of the three blocks has three protection bits associated with them. they are: code-protect bit (cpn) write-protect bit (wrtn) external block table read bit (ebtrn) figure 19-5 shows the program memory organization for 4 and 8-kbyte devices and the specific code protec- tion bit associated with each block. the actual locations of the bits are summarized in tab l e 1 9- 3 . figure 19-5: code-protected prog ram memory for pic18f1220/1320 table 19-3: summary of code protection registers block code protection controlled by: memory size/device block code protection controlled by: address range 4kbytes (pic18f1220) 8kbytes (pic18f1320) address range cpb, wrtb, ebtrb 000000h 0001ffh boot block boot block 000000h 0001ffh cpb, wrtb, ebtrb cp0, wrt0, ebtr0 000200h 0007ffh block 0 block 0 000200h cp0, wrt0, ebtr0 cp1, wrt1, ebtr1 000800h 000fffh block 1 000fffh (unimplemented memory space) 001000h unimplemented read 0 s block 1 001000h cp1, wrt1, ebtr1 001fffh 1fffffh unimplemented read 0 s 002000h 1fffffh (unimplemented memory space) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300008h config5l c p 1c p 0 300009h config5h cpd cpb 30000ah config6l wrt1 wrt0 30000bh config6h wrtd wrtb wrtc 30000ch config7l ebtr1 ebtr0 30000dh config7h ebtrb legend: shaded cells are unimplemented. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 180 ? 2002-2015 microchip technology inc. 19.5.1 program memory code protection the program memory may be read to, or written from, any location using the table read and table write instructions. the device id may be read with table reads. the configuration registers may be read and written with the table read and table write instructions. in normal execution mode, the cpn bits have no direct effect. cpn bits inhibit external reads and writes. a block of user memory may be protected from table writes if the wrtn configuration bit is 0 . the ebtrn bits control table reads. for a block of user memory with the ebtrn bit set to 0 , a table read instruction that executes from within that block is allowed to read. a table read instruction that executes from a location outside of that block is not allowed to read and will result in reading 0 s. figures 19-6 through 19-8 illustrate table write and table read protection. figure 19-6: table write (wr tn) disallowed: pic18f1320 note: code protection bits may only be written to a 0 from a 1 state. it is not possible to write a 1 to a bit in the 0 state. code pro- tection bits are only set to 1 by a full chip erase or block erase function. the full chip erase and block erase functions can only be initiated via icsp or an external programmer. 000000h 0001ffh 000200h 000fffh 001000h 001fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 01 tblwt * tblptr = 0002ffh pc = 0007feh tblwt * pc = 0017feh register values program memory configuration bit settings results: all table writes disabled to blockn whenever wrtn = 0 . wrt1, ebtr1 = 11 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 181 pic18f1220/1320 figure 19-7: external bl ock table read (ebtrn) disallowed: pic18f1320 figure 19-8: external bl ock table read (ebtrn ) allowed: pic18f1320 000000h 0001ffh 000200h 000fffh 001000h 001fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 tblptr = 0002ffh register values program memory configuration bit settings pc = 001ffeh tblrd * results: all table reads from external blocks to blockn are disabled whenever ebtrn = 0 . tablat register returns a value of 0 . 000000h 0001ffh 000200h 000fffh 001000h 001fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 tblrd * tblptr = 0002ffh pc = 0007feh register values program memory configuration bit settings results: table reads permitted within blockn, even when ebtrbn = 0 . tablat register returns the value of the data at the location tblptr. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 182 ? 2002-2015 microchip technology inc. 19.5.2 data eeprom code protection the entire data eeprom is protected from external reads and writes by two bits: cpd and wrtd. cpd inhibits external reads and writes of data eeprom. wrtd inhibits external writes to data eeprom. the cpu can continue to read and write data eeprom, regardless of the protection bit settings. 19.5.3 configuration register protection the configuration registers can be write-protected. the wrtc bit controls protection of the configuration registers. in normal execution mode, the wrtc bit is readable only. wrtc can only be written via icsp or an external programmer. 19.6 id locations eight memory locations (200000h-200007h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are both readable and writable during normal execution through the tblrd and tblwt instructions, or during program/verify. the id locations can be read when the device is code-protected. 19.7 in-circuit serial programming pic18f1220/1320 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed (see table 19-4 ). 19.8 in-circuit debugger when the debug bit in configuration register, config4l, is programmed to a 0 , the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. ta b l e 1 9 - 5 shows which resources are required by the background debugger. table 19-5: debugger resources to use the in-circuit debugger function of the microcontroller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , v ss , rb7 and rb6. this will interface to the in-circuit debugger module available from microchip, or one of the third party development tool companies (see the note fol- lowing section 19.7 ?in-circuit serial programming? for more information). note: the timer1 oscillator shares the t1osi and t1oso pins with the pgd and pgc pins used for programming and debugging. when using the timer1 oscillator, in-circuit serial programming (icsp) may not function correctly (high voltage or low voltage), or the in-circuit debugger (icd) may not communicate with the controller. as a result of using either icsp or icd, the timer1 crystal may be damaged. if icsp or icd operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. the oscillator loading capacitors may remain in-circuit during icsp or icd operation. table 19-4: icsp/icd connections signal pin notes pgd rb7/pgd/t1osi/ p1d/kbi3 shared with t1osc C protect crystal pgc rb6/pgc/t1oso/ t13cki/p1c/kbi2 shared with t1osc C protect crystal mclr mclr /v pp /ra5 v dd v dd v ss v ss pgm rb5/pgm/kbi1 optional C pull rb5 low is lvp enabled i/o pins: rb6, rb7 stack: 2 levels program memory: 512 bytes data memory: 10 bytes downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 183 pic18f1220/1320 19.9 low-voltage icsp programming the lvp bit in configuration register, config4l, enables low-voltage programming (lvp). when lvp is enabled, the microcontroller can be programmed without requiring high voltage being applied to the mclr /v pp /ra5 pin, but the rb5/pgm/kbi1 pin is then dedicated to controlling program mode entry and is not available as a general purpose i/o pin. lvp is enabled in erased devices. while programming using lvp, v dd is applied to the mclr /v pp /ra5 pin as in normal execution mode. to enter programming mode, v dd is applied to the pgm pin. if low-voltage programming mode will not be used, the lvp bit can be cleared and rb5/pgm/kbi1 becomes available as the digital i/o pin rb5. the lvp bit may be set or cleared only when using standard high-voltage programming (v ihh applied to the mclr /v pp /ra5 pin). once lvp has been disabled, only the standard high- voltage programming is available and must be used to program the device. memory that is not code-protected can be erased, using either a block erase, or erased row by row, then written at any specified v dd . if code-protected memory is to be erased, a block erase is required. if a block erase is to be performed when using low-voltage programming, the device must be supplied with v dd of 4.5v to 5.5v. note 1: high-voltage programming is always available, regardless of the state of the lvp bit or the pgm pin, by applying v ihh to the mclr pin. 2: when low-voltage programming is enabled, the rb5 pin can no longer be used as a general purpose i/o pin. 3: when lvp is enabled, externally pull the pgm pin to v ss to allow normal program execution. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 184 ? 2002-2015 microchip technology inc. 20.0 instruction set summary the pic18 instruction set adds many enhancements to the previous pic instruction sets, while maintaining an easy migration from these pic instruction sets. most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18 instruction set summary in table 20-1 lists byte-oriented , bit-oriented , literal and control operations. tab l e 2 0- 1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by f) 2. the destination of the result (specified by d) 3. the accessed memory (specified by a) the file register designator f specifies which file register is to be used by the instruction. the destination designator d specifies where the result of the operation is to be placed. if d is zero, the result is placed in the wreg register. if d is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by f) 2. the bit in the file register (specified by b) 3. the accessed memory (specified by a) the bit field designator b selects the number of the bit affected by the operation, while the file register desig- nator f represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by k) the desired fsr register to load the literal value into (specified by f) no operand required (specified by ) the control instructions may use some of the following operands: a program memory address (specified by n) the mode of the call or return instructions (specified by s) the mode of the table read and table write instructions (specified by m) no operand required (specified by ) all instructions are a single word, except for three double-word instructions. these three instructions were made double-word instructions so that all the required information is available in these 32 bits. in the second word, the 4 msbs are 1 s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop . the double-word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. two-word branch instructions (if true) would take 3 ? s. figure 20-1 shows the general formats that the instructions can have. all examples use the format nnh to represent a hexa- decimal number, where h signifies a hexadecimal digit. the instruction set summary, shown in table 20-1 , lists the instructions recognized by the microchip assembler (mpasm tm ). section 20.2 ?instruction set? provides a description of each instruction. 20.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified and the result is stored according to either the instruction or the destination designator d. a read operation is performed on a register even if the instruction writes to that register. for example, a bcf portb,1 instruction will read portb, clear bit 1 of the data, then write the result back to portb. the read operation would have the unintended result that any condition that sets the rbif flag would be cleared. the r-m-w operation may also copy the level of an input pin to its corresponding output latch. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 185 pic18f1220/1320 table 20-1: opcode field descriptions field description a ram access bit a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. d destination select bit d = 0 : store result in wreg d = 1 : store result in file register f dest destination either the wreg register or the specified register file location. f 8-bit register file address (0x00 to 0xff). fs 12-bit register file address (0x000 to 0xfff). this is the source address. fd 12-bit register file address (0x000 to 0xfff). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tb lptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2s complement number) for relative branch instructions, or the direct address for call/branch and return instructions. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) u unused or unchanged. wreg working register (accumulator). x dont care ( 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. tos top-of-stack. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. gie global interrupt enable bit. wdt watchdog timer. to time-out bit. pd power-down bit. c, dc, z, ov, n alu status bits: carry, digit carry, zero, overflow, negative. [ ] optional. ( ) contents. ? assigned to. < > register bit field. ? in the set of. italics user defined term (font is courier). downloaded from: http:///
pic18f1220/1320 ds30009605g-page 186 ? 2002-2015 microchip technology inc. figure 20-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 0x7f goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 187 pic18f1220/1320 table 20-1: pic18fxxxx instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 11 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 00100010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffffffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffffffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 21, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 bit-oriented file register operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, d, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 11 1 (2 or 3) 1 (2 or 3) 1 10011000 1011 1010 0111 bbbabbba bbba bbba bbba ffffffff ffff ffff ffff ffffffff ffff ffff ffff none none none none none 1, 21, 2 3, 4 3, 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0 . 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instru ctions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 188 ? 2002-2015 microchip technology inc. control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep nn n n n n n n n n, s n n s k s branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 11101110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 00100110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnnnnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnnnnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 20-1: pic18fxxxx instru ction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0 . 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 189 pic18f1220/1320 literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw kk k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsrx 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 11 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 11111011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkkkkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkkkkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment tab l e w r i t e table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 00000000 0000 0000 0000 0000 00000000 00000000 0000 0000 0000 0000 0000 0000 10001001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 20-1: pic18fxxxx instru ction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0 . 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instru ctions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 190 ? 2002-2015 microchip technology inc. 20.2 instruction set addlw add literal to w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal k and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example : addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w to f syntax: [ label ] addwf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) + (f) ? dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected. if a is 1 , the bsr is used. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : addwf reg, w before instruction w = 0x17 reg = 0xc2 after instruction w=0 x d 9 reg = 0xc2 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 191 pic18f1220/1320 addwfc add w and carry bit to f syntax: [ label ] addwfc f [,d [,a]] operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: n, ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location f. if d is 0 , the result is placed in w. if d is 1 , the result is placed in data memory location f. if a is 0 , the access bank will be selected. if a is 1 , the bsr will not be overridden. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : addwfc reg, w before instruction carry bit = 1 reg = 0x02 w = 0x4d after instruction carry bit = 0 reg = 0x02 w = 0x50 andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. k ? w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example : andlw 0x5f before instruction w=0 x a 3 after instruction w = 0x03 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 192 ? 2002-2015 microchip technology inc. andwf and w with f syntax: [ label ] andwf f [,d [,a]] operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (w) .and. (f) ? dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are anded with register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected. if a is 1 , the bsr will not be overridden (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : andwf reg, w before instruction w = 0x17 reg = 0xc2 after instruction w = 0x02 reg = 0xc2 bc branch if carry syntax: [ label ] bc n operands: -128 ? n ? 127 operation: if carry bit is 1 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bc jump before instruction pc = address (here) after instruction if carry = 1; pc = address (jump) if carry = 0; pc = address (here + 2) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 193 pic18f1220/1320 bcf bit clear f syntax: [ label ] bcf f,b[,a] operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 0 ? f status affected: none encoding: 1001 bbba ffff ffff description: bit b in register f is cleared. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example : bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bn branch if negative syntax: [ label ] bn n operands: -128 ? n ? 127 operation: if negative bit is 1 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here + 2) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 194 ? 2002-2015 microchip technology inc. bnc branch if not carry syntax: [ label ] bnc n operands: -128 ? n ? 127 operation: if carry bit is 0 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here + 2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 ? n ? 127 operation: if negative bit is 0 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here + 2) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 195 pic18f1220/1320 bnov branch if not overflow syntax: [ label ] bnov n operands: -128 ? n ? 127 operation: if overflow bit is 0 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here + 2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 ? n ? 127 operation: if zero bit is 0 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is 0 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here + 2) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 196 ? 2002-2015 microchip technology inc. bra unconditional branch syntax: [ label ] bra n operands: -1024 ? n ? 1023 operation: (pc) + 2 + 2n ? pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2s complement number 2n to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a 2- cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation example : here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f,b[,a] operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 1 ? f status affected: none encoding: 1000 bbba ffff ffff description: bit b in register f is set. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example : bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 197 pic18f1220/1320 btfsc bit test file, skip if clear syntax: [ label ] btfsc f,b[,a] operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit b in register f is 0 , then the next instruction is skipped. if bit b is 0 , then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a 2-cycle instruction. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfsc: : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f,b[,a] operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit b in register f is 1 , then the next instruction is skipped. if bit b is 1 , then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a 2-cycle instruction. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : herefalse true btfss: : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 198 ? 2002-2015 microchip technology inc. btg bit toggle f syntax: [ label ] btg f,b[,a] operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: (f ) ? f status affected: none encoding: 0111 bbba ffff ffff description: bit b in data memory location f is inverted. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example : btg portb, 4 before instruction: portb = 0111 0101 [0x75] after instruction: portb = 0110 0101 [0x65] bov branch if overflow syntax: [ label ] bov n operands: -128 ? n ? 127 operation: if overflow bit is 1 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here + 2) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 199 pic18f1220/1320 bz branch if zero syntax: [ label ] bz n operands: -128 ? n ? 127 operation: if zero bit is 1 (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is 1 , then the program will branch. the 2s complement number 2n is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a 2-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal n process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal n process data no operation example : here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here + 2) call subroutine call syntax: [ label ] call k [,s] operands: 0 ? k ? 1048575 s ?? [0,1] operation: (pc) + 4 ? tos, k ? pc<20:1>, if s = 1 (w) ? ws, (status) ? statuss, (bsr) ? bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 11101111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc + 4) is pushed onto the return stack. if s = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if s = 0 , no update occurs (default). then, the 20-bit value k is loaded into pc<20:1>. call is a 2-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k<7:0>, push pc to stack read literal k<19:8>, write to pc no operation no operation no operation no operation example : here call there, fast before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss = status downloaded from: http:///
pic18f1220/1320 ds30009605g-page 200 ? 2002-2015 microchip technology inc. clrf clear f syntax: [ label ] clrf f [,a] operands: 0 ? f ? 255 a ?? [0,1] operation: 000h ? f 1 ? z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example : clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h ? wdt, 000h ? wdt postscaler, 1 ? to, 1 ? pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt postscaler = 0 to =1 pd =1 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 201 pic18f1220/1320 comf complement f syntax: [ label ] comf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f ) ? dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register f are complemented. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : comf reg, w before instruction reg = 0x13 after instruction reg = 0x13 w=0 x e c cpfseq compare f with w, skip if f = w syntax: [ label ] cpfseq f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (f) C (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location f to the contents of w by performing an unsigned subtraction. if f = w , then the fetched instruction is discarded and a nop is executed instead, making this a 2-cycle instruction. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfseq reg nequal : equal : before instruction pc address = here w= ? reg = ? after instruction if reg = w; pc = address (equal) if reg ? w; pc = address (nequal) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 202 ? 2002-2015 microchip technology inc. cpfsgt compare f with w, skip if f > w syntax: [ label ] cpfsgt f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (f) C ?? w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location f to the contents of w by performing an unsigned subtraction. if the contents of f are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a 2-cycle instruction. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfsgt reg ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg ? w; pc = address (greater) if reg ? w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: [ label ] cpfslt f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (f) C ?? w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location f to the contents of w by performing an unsigned subtraction. if the contents of f are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a 2-cycle instruction. if a is 0 , the access bank will be selected. if a is 1 , the bsr will not be overridden (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfslt reg nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg ? w; pc = address (nless) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 203 pic18f1220/1320 daw decimal adjust w register syntax: [ label ] daw operands: none operation: if [w<3:0> > 9] or [dc = 1 ] then (w<3:0>) + 6 ? w<3:0>; else ( w<3:0>) ? w<3:0>; if [w<7:4> > 9] or [c = 1 ] then ( w<7:4>) + 6 ? w<7:4>; else (w<7:4>) ? w<7:4>; status affected: c, dc encoding: 0000 0000 0000 0111 description: daw adjusts the 8-bit value in w, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. the carry bit may be set by daw regardless of its setting prior to the daw instruction. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example 1 : daw before instruction w=0 x a 5 c= 0 dc = 0 after instruction w = 0x05 c= 1 dc = 0 example 2 : before instruction w=0 x c e c= 0 dc = 0 after instruction w = 0x34 c= 1 dc = 0 decf decrement f syntax: [ label ] decf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C 1 ? dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : decf cnt before instruction cnt = 0x01 z= 0 after instruction cnt = 0x00 z= 1 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 204 ? 2002-2015 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C 1 ? dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register f are decremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if the result is 0 , the next instruc- tion, which is already fetched, is discarded and a nop is executed instead, making it a 2-cycle instruc- tion. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here decfsz cnt goto loop continue before instruction pc = address (here) after instruction cnt = cnt C 1 if cnt = 0; pc = address (continue) if cnt ? 0; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register f are decremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if the result is not 0 , the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a 2- cycle instruction. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here dcfsnz temp zero : nzero : before instruction temp = ? after instruction temp = temp C 1, if temp = 0; pc = address (zero ) if temp ? 0; pc = address (nzero) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 205 pic18f1220/1320 goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 1048575 operation: k ? pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 11101111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within the entire 2-mbyte memory range. the 20-bit value k is loaded into pc<20:1>. goto is always a 2-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k<7:0>, no operation read literal k<19:8>, write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register f are incremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : incf cnt before instruction cnt = 0xff z= 0 c= ? dc = ? after instruction cnt = 0x00 z= 1 c= 1 dc = 1 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 206 ? 2002-2015 microchip technology inc. incfsz increment f, skip if 0 syntax: [ label ] incfsz f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register f are incremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if the result is 0 , the next instruc- tion, which is already fetched, is discarded and a nop is executed instead, making it a 2-cycle instruc- tion. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here incfsz cnt nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt ? 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register f are incremented. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if the result is not 0 , the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a 2- cycle instruction. if a is 0 , the access bank will be selected, over- riding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here infsnz reg zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg ? 0; pc = address (nzero) if reg = 0; pc = address (zero) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 207 pic18f1220/1320 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the 8-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example : iorlw 0x35 before instruction w = 0x9a after instruction w=0 x b f iorwf inclusive or w with f syntax: [ label ] iorwf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) .or. (f) ? dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register f. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if a is 0 , the access bank will be selected, over- riding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : iorwf result, w before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 208 ? 2002-2015 microchip technology inc. lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 ? f ? 2 0 ? k ? 4095 operation: k ? fsrf status affected: none encoding: 11101111 11100000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal k is loaded into the file select register pointed to by f. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k msb process data write literal k msb to fsrfh decode read literal k lsb process data write literal k to fsrfl example : lfsr 2, 0x3ab after instruction fsr2h = 0x03 fsr2l = 0xab movf move f syntax: [ label ] movf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: f ? dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register f are moved to a destination dependent upon the status of d. if d is f, the result is placed in w. if d is f, the result is placed back in register f (default). location f can be any- where in the 256-byte bank. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write w example : movf reg, w before instruction reg = 0x22 w= 0 x f f after instruction reg = 0x22 w = 0x22 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 209 pic18f1220/1320 movff move f to f syntax: [ label ] movff f s ,f d operands: 0 ? f s ? 4095 0 ? f d ? 4095 operation: (f s ) ? f d status affected: none encoding: 1st word (source) 2nd word (destin.) 11001111 ffffffff ffffffff fff f s fff f d description: the contents of source register f s are moved to destination register f d . location of source f s can be anywhere in the 4096-byte data space (000h to fffh) and location of destination f d can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. the movff instruction should not be used to modify interrupt settings while any interrupt is enabled (see page 70). words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register f (src) process data no operation decode no operation no dummy read no operation write register f (dest) example : movff reg1, reg2 before instruction reg1 = 0x33 reg2 = 0x11 after instruction reg1 = 0x33, reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 ? k ? 255 operation: k ? bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal k is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write literal k to bsr example : movlb 5 before instruction bsr register = 0x02 after instruction bsr register = 0x05 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 210 ? 2002-2015 microchip technology inc. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? w status affected: none encoding: 0000 1110 kkkk kkkk description: the 8-bit literal k is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example : movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (w) ? f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register f. location f can be anywhere in the 256-byte bank. if a is 0 , the access bank will be selected, over- riding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example : movwf reg before instruction w = 0x4f reg = 0xff after instruction w = 0x4f reg = 0x4f downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 211 pic18f1220/1320 mullw multiply literal with w syntax: [ label ] mullw k operands: 0 ? k ? 255 operation: (w) x k ? prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal k. the 16-bit result is placed in the prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write registers prodh: prodl example : mullw 0xc4 before instruction w= 0 x e 2 prodh = ? prodl = ? after instruction w= 0 x e 2 prodh = 0xad prodl = 0x08 mulwf multiply w with f syntax: [ label ] mulwf f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (w) x (f) ? prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location f. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and f are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible, but not detected. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write registers prodh: prodl example : mulwf reg before instruction w= 0 x c 4 reg = 0xb5 prodh = ? prodl = ? after instruction w= 0 x c 4 reg = 0xb5 prodh = 0x8a prodl = 0x94 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 212 ? 2002-2015 microchip technology inc. negf negate f syntax: [ label ] negf f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (f ) + 1 ? f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location f is negated using twos complement. the result is placed in the data memory location f. if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example : negf reg, 1 before instruction reg = 0011 1010 [0x3a] after instruction reg = 1100 0110 [0xc6] nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00001111 0000xxxx 0000xxxx 0000xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 213 pic18f1220/1320 pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) ? bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example : pop goto new before instruction tos = 0x0031a2 stack (1 level down) = 0x014332 after instruction tos = 0x014332 pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc + 2) ? tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implement- ing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example : push before instruction tos = 0x00345a pc = 0x000124 after instruction pc = 0x000126 tos = 0x000126 stack (1 level down) = 0x00345a downloaded from: http:///
pic18f1220/1320 ds30009605g-page 214 ? 2002-2015 microchip technology inc. rcall relative call syntax: [ label ] rcall n operands: -1024 ? n ? 1023 operation: (pc) + 2 ? tos, (pc) + 2 + 2n ? pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2s complement number 2n to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a 2-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal n push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 215 pic18f1220/1320 retfie return from interrupt syntax: [ label ] retfie [s] operands: s ? [0,1] operation: (tos) ? pc, 1 ? gie/gieh or peie/giel, if s = 1 (ws) ? w, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged. status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if s = 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corresponding registers, w, status and bsr. if s = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example : retfie 1 after interrupt pc = tos w= w s bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? w, (tos) ? pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the 8-bit literal k. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal k process data pop pc from stack, write to w no operation no operation no operation no operation example : call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 0x07 after instruction w = value of kn downloaded from: http:///
pic18f1220/1320 ds30009605g-page 216 ? 2002-2015 microchip technology inc. return return from subroutine syntax: [ label ] return [s] operands: s ? [0,1] operation: (tos) ? pc, if s = 1 (ws) ? w, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack is loaded into the program counter. if s= 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corre- sponding registers, w, status and bsr. if s = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after interrupt pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<7>) ? c, (c) ? dest<0> status affected: c, n, z encoding: 0011 01da ffff ffff description: the contents of register f are rotated one bit to the left through the carry flag. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : rlcf reg, w before instruction reg = 1110 0110 c= 0 after instruction reg = 1110 0110 w = 1100 1100 c= 1 c register f downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 217 pic18f1220/1320 rlncf rotate left f (no carry) syntax: [ label ] rlncf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<7>) ? dest<0> status affected: n, z encoding: 0100 01da ffff ffff description: the contents of register f are rotated one bit to the left. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : rlncf reg before instruction reg = 1010 1011 after instruction reg = 0101 0111 register f rrcf rotate right f through carry syntax: [ label ] rrcf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<0>) ? c, (c) ? dest<7> status affected: c, n, z encoding: 0011 00da ffff ffff description: the contents of register f are rotated one bit to the right through the carry flag. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : rrcf reg, w before instruction reg = 1110 0110 c= 0 after instruction reg = 1110 0110 w = 0111 0011 c= 0 c register f downloaded from: http:///
pic18f1220/1320 ds30009605g-page 218 ? 2002-2015 microchip technology inc. rrncf rotate right f (no carry) syntax: [ label ] rrncf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<0>) ? dest<7> status affected: n, z encoding: 0100 00da ffff ffff description: the contents of register f are rotated one bit to the right. if d is 0 , the result is placed in w. if d is 1 , the result is placed back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1 : rrncf reg, 1, 0 before instruction reg = 1101 0111 after instruction reg = 1110 1011 example 2 : rrncf reg, w before instruction w=? reg = 1101 0111 after instruction w = 1110 1011 reg = 1101 0111 register f setf set f syntax: [ label ] setf f [,a] operands: 0 ? f ? 255 a ?? [0,1] operation: ffh ? f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified register are set to ffh. if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write register f example : setf reg before instruction reg = 0x5a after instruction reg = 0xff downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 219 pic18f1220/1320 sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt postscaler, 1 ? to , 0 ? pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. the watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to = 1 ? pd = 0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: [ label ] subfwb f [,d [,a]] operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (w) C (f) C (c ) ?? dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register f and carry flag (borrow) from w (2s complement method). if d is 0 , the result is stored in w. if d is 1 , the result is stored in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1 : subfwb reg before instruction reg = 0x03 w = 0x02 c = 0x01 after instruction reg = 0xff w = 0x02 c = 0x00 z = 0x00 n = 0x01 ; result is negative example 2 : subfwb reg, 0, 0 before instruction reg = 2 w=5 c= 1 after instruction reg = 2 w=3 c= 1 z= 0 n = 0 ; result is positive example 3 : subfwb reg, 1, 0 before instruction reg = 1 w=2 c= 0 after instruction reg = 0 w=2 c= 1 z= 1; r e s u l t i s z e r o n= 0 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 220 ? 2002-2015 microchip technology inc. sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k C (w) ?? w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the 8-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example 1: sublw 0x02 before instruction w=1 c= ? after instruction w=1 c = 1 ; result is positive z= 0 n= 0 example 2 : sublw 0x02 before instruction w=2 c= ? after instruction w=0 c = 1 ; result is zero z= 1 n= 0 example 3 : sublw 0x02 before instruction w=3 c= ? after instruction w = ff ; (2s complement) c = 0 ; result is negative z= 0 n= 1 subwf subtract w from f syntax: [ label ] subwf f [,d [,a]] operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (f) C (w) ?? dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register f (2s complement method). if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1 : subwf reg before instruction reg = 3 w=2 c= ? after instruction reg = 1 w=2 c = 1 ; result is positive z= 0 n= 0 example 2 : subwf reg, w before instruction reg = 2 w=2 c= ? after instruction reg = 2 w=0 c = 1 ; result is zero z= 1 n= 0 example 3 : subwf reg before instruction reg = 0x01 w = 0x02 c= ? after instruction reg = 0xffh ;(2s complement) w = 0x02 c = 0x00 ;result is negative z = 0x00 n = 0x01 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 221 pic18f1220/1320 subwfb subtract w from f with borrow syntax: [ label ] subwfb f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) C (w) C (c ) ?? dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register f (2s comple- ment method). if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example 1 : subwfb reg, 1, 0 before instruction reg = 0x19 ( 0001 1001 ) w = 0x0d ( 0000 1101 ) c = 0x01 after instruction reg = 0x0c ( 0000 1011 ) w = 0x0d ( 0000 1101 ) c = 0x01 z = 0x00 n = 0x00 ; result is positive example 2 : subwfb reg, 0, 0 before instruction reg = 0x1b ( 0001 1011 ) w = 0x1a ( 0001 1010 ) c = 0x00 after instruction reg = 0x1b ( 0001 1011 ) w = 0x00 c = 0x01 z = 0x01 ; result is zero n = 0x00 example 3: subwfb reg, 1, 0 before instruction reg = 0x03 ( 0000 0011 ) w = 0x0e ( 0000 1101 ) c = 0x01 after instruction reg = 0xf5 ( 1111 0100 ) ; [2s comp] w = 0x0e ( 0000 1101 ) c = 0x00 z = 0x00 n = 0x01 ; result is negative swapf swap f syntax: [ label ] swapf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f<3:0>) ? dest<7:4>, (f<7:4>) ? dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register f are exchanged. if d is 0 , the result is placed in w. if d is 1 , the result is placed in register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : swapf reg before instruction reg = 0x53 after instruction reg = 0x35 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 222 ? 2002-2015 microchip technology inc. tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) ? tablat; tblptr C no change; if tblrd *+, (prog mem (tblptr)) ? tablat; (tblptr) + 1 ? tblptr; if tblrd *-, (prog mem (tblptr)) ? tablat; (tblptr) C 1 ? tblptr; if tblrd +*, (tblptr) + 1 ? tblptr; (prog mem (tblptr)) ? tablat; status affected: none encoding: 0000 0000 0000 10nn nn = 0* = 1*+ = 2*- = 3+* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr[0] = 0 :least significant byte of program memory word tblptr[0] = 1 :most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (continued) example 1 : tblrd *+ ; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0x34 after instruction tablat = 0x34 tblptr = 0x00a357 example 2 : tblrd +* ; before instruction tablat = 0xaa tblptr = 0x01a357 memory(0x01a357) = 0x12 memory(0x01a358) = 0x34 after instruction tablat = 0x34 tblptr = 0x01a358 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 223 pic18f1220/1320 tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) ? holding register; tblptr C no change; if tblwt*+, (tablat) ? holding register; (tblptr) + 1 ? tblptr; if tblwt*-, (tablat) ? holding register; (tblptr) C 1 ? tblptr; if tblwt+*, (tblptr) + 1 ? tblptr; (tablat) ? holding register; status affected: none encoding: 0000 0000 0000 11nn nn = 0* = 1*+ = 2*- = 3+* description: this instruction uses the 3 lsbs of tblptr to determine which of the eight holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 6.0 ?flash program memory? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 :least significant byte of program memory word tblptr[0] = 1 :most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment tblwt table write (continued) words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register) example 1 : tblwt *+; before instruction tablat = 0x55 tblptr = 0x00a356 holding register (0x00a356) = 0xff after instructions (table write completion) tablat = 0x55 tblptr = 0x00a357 holding register (0x00a356) = 0x55 example 2 : tblwt +*; before instruction tablat = 0x34 tblptr = 0x01389a holding register (0x01389a) = 0xff holding register (0x01389b) = 0xff after instruction (table write completion) tablat = 0x34 tblptr = 0x01389b holding register (0x01389a) = 0xff holding register (0x01389b) = 0x34 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 224 ? 2002-2015 microchip technology inc. tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if f = 0 , the next instruction, fetched during the current instruction execution is discarded and a nop is executed, making this a 2-cycle instruction. if a is 0 , the access bank will be selected, over- riding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register f process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here tstfsz cnt nzero : zero : before instruction pc = address ( here ) after instruction if cnt = 0x00, pc = address (zero) if cnt ? 0x00, pc = address (nzero) xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ?? w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal k. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal k process data write to w example : xorlw 0xaf before instruction w=0 x b 5 after instruction w = 0x1a downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 225 pic18f1220/1320 xorwf exclusive or w with f syntax: [ label ] xorwf f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) .xor. (f) ?? dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register f. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in the register f (default). if a is 0 , the access bank will be selected, overriding the bsr value. if a is 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register f process data write to destination example : xorwf reg before instruction reg = 0xaf w=0 x b 5 after instruction reg = 0x1a w=0 x b 5 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 226 ? 2002-2015 microchip technology inc. 21.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: integrated development environment - mplab ? x ide software compilers/assemblers/linkers - mplab xc compiler -mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families simulators - mplab x sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 device programmers - mplab pm3 device programmer low-cost demonstration/development boards, evaluation kits and starter kits third-party development tools 21.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: color syntax highlighting smart code completion makes suggestions and provides hints as you type automatic code formatting based on user-defined rules live parsing user-friendly, customizable interface: fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. call graph window project-based workspaces: multiple projects multiple tools multiple configurations simultaneous debugging sessions file history and bug tracking: local file history feature built-in support for bugzilla issue tracker downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 227 pic18f1220/1320 21.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchips 8, 16, and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo- catable object files and archives to create an execut- able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem- bler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility 21.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: integration into mplab x ide projects user-defined macros to streamline assembly code conditional assembly for multipurpose source files directives that allow complete control over the assembly process 21.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 21.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility downloaded from: http:///
pic18f1220/1320 ds30009605g-page 228 ? 2002-2015 microchip technology inc. 21.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 21.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 21.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchips most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineers pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 21.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineers pc using a full- speed usb interface and can be connected to the tar- get via a microchip debug (rj-11) connector (compati- ble with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 21.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 229 pic18f1220/1320 21.11 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 21.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. device programmers and gang programmers from companies, such as softlog and ccs software tools from companies, such as gimpel and trace systems protocol analyzers from companies, such as saleae and total phase demonstration boards from companies, such as mikroelektronika, digilent ? and olimex embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ? downloaded from: http:///
pic18f1220/1320 ds30009605g-page 230 ? 2002-2015 microchip technology inc. 22.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias ................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr and ra4)........................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +5.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to vss ............................................................................................. .................. 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... .1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ???????????????????????????????????????????????????????????????????????????????????????????????????? ?????????????????? ? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ???????????????????????????????????????????????????????????????????????????????????????????????????? ?????????? ? 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin.................................................................................. ...................25 ma maximum current sunk by ? all ports........................................................................................................................200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd C ? i oh } + ? {(v dd C v oh ) x i oh } + ? (v ol x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a low level to the mclr /v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 231 pic18f1220/1320 figure 22-1: pic18f1220/1320 voltage-freque ncy graph (industrial) figure 22-2: pic18lf1220/1320 voltage- frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18f1x20 4.2v frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v f max = (16.36 mhz/v) (v ddappmin C 2.0v) + 4 mhz note: v ddappmin is the minimum voltage of the pic ? device in the application. 4 mhz 4.2v pic18lf1x20 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 232 ? 2002-2015 microchip technology inc. figure 22-3: pic18f1220/1320 voltage-frequency graph (extended) frequency voltage 6.0v5.5v 4.5v 4.0v 2.0v 25 mhz 5.0v3.5v 3.0v 2.5v pic18f1x20-e 4.2v downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 233 pic18f1220/1320 22.1 dc characteristics: supply voltage pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ. max. units conditions v dd supply voltage d001 pic18lf1220/1320 2.0 5.5 v hs, xt, rc and lp oscillator mode pic18f1220/1320 4.2 5.5 v d002 v dr ram data retention voltage (1) 1.5 v d003 v por v dd start voltage to ensure internal power-on reset signal 0.7 v see section 4.1 ?power-on reset (por)? for details. d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section 4.1 ?power-on reset (por)? for details. v bor brown-out reset voltage d005d pic18lf1220/1320 industrial low voltage (-10 ? c to +85 ? c) borv1:borv0 = 11 n/a n/a n/a v reserved borv1:borv0 = 10 2.50 2.72 2.94 v borv1:borv0 = 01 3.88 4.22 4.56 v (note 2) borv1:borv0 = 00 4.18 4.54 4.90 v (note 2) d005f pic18lf1220/1320 industrial low voltage (-40 ? c to -10 ? c) borv1:borv0 = 11 n/a n/a n/a v reserved borv1:borv0 = 10 2.34 2.72 3.10 v borv1:borv0 = 01 3.63 4.22 4.81 v (note 2) borv1:borv0 = 00 3.90 4.54 5.18 v (note 2) d005g pic18f1220/1320 industrial (-10 ? c to +85 ? c) borv1:borv0 = 1x n/a n/a n/a v reserved borv1:borv0 = 01 3.88 4.22 4.56 v (note 2) borv1:borv0 = 00 4.18 4.54 4.90 v (note 2) d005h pic18f1220/1320 industrial (-40 ? c to -10 ? c) borv1:borv0 = 1x n/a n/a n/a v reserved borv1:borv0 = 01 n/a n/a n/a v reserved borv1:borv0 = 00 3.90 4.54 5.18 v (note 2) d005j pic18f1220/1320 extended (-10 ? c to +85 ? c) borv1:borv0 = 1x n/a n/a n/a v reserved borv1:borv0 = 01 3.88 4.22 4.56 v (note 3) borv1:borv0 = 00 4.18 4.54 4.90 v (note 3) d005k pic18f1220/1320 extended (-40 ? c to -10 ? c, +85 ? c to +125 ? c) borv1:borv0 = 1x n/a n/a n/a v reserved borv1:borv0 = 01 n/a n/a n/a v reserved borv1:borv0 = 00 3.90 4.54 5.18 v (note 3) legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: when bor is on and borv<1:0> = 0x , the device will operate correctly at 40 mhz for any v dd at which the bor allows execution (low-voltage and industrial devices only). 3: when bor is on and borv<1:0> = 0x , the device will operate correctly at 25 mhz for any v dd at which the bor allows execution (extended devices only). downloaded from: http:///
pic18f1220/1320 ds30009605g-page 234 ? 2002-2015 microchip technology inc. 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions power-down current (i pd ) (1) pic18lf1220/1320 0.1 0.5 ? a -40c v dd = 2.0v, ( sleep mode) 0.1 0.5 ? a +25c 0.2 1.9 ? a +85c pic18lf1220/1320 0.1 0.5 ? a -40c v dd = 3.0v, ( sleep mode) 0.1 0.5 ? a+ 2 5 c 0.3 1.9 ? a +85c all devices 0.1 2.0 ? a -40c v dd = 5.0v, ( sleep mode) 0.1 2.0 ? a +25c 0.4 6.5 ? a +85c extended devices 11.2 50 ? a +125c supply current (i dd ) (2,3) pic18lf1220/1320 8 40 ? a -40c f osc = 31 khz ( rc_run mode, internal oscillator source) 94 0 ? a+ 2 5 c v dd = 2.0v 11 40 ? a+ 8 5 c pic18lf1220/1320 25 68 ? a -40c 25 68 ? a+ 2 5 c v dd = 3.0v 20 68 ? a+ 8 5 c all devices 55 80 ? a -40c v dd = 5.0v 55 80 ? a+ 2 5 c 50 80 ? a+ 8 5 c extended devices 50 80 ? a +125c legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 235 pic18f1220/1320 supply current (i dd ) (2,3) pic18lf1220/1320 140 220 ? a -40c f osc = 1 mhz ( rc_run mode, internal oscillator source) 145 220 ? a+ 2 5 c v dd = 2.0v 155 220 ? a+ 8 5 c pic18lf1220/1320 215 330 ? a -40c 225 330 ? a+ 2 5 c v dd = 3.0v 235 330 ? a+ 8 5 c all devices 385 550 ? a -40c v dd = 5.0v 390 550 ? a+ 2 5 c 405 550 ? a+ 8 5 c extended devices 410 650 ? a +125c pic18lf1220/1320 410 600 ? a -40c f osc = 4 mhz ( rc_run mode, internal oscillator source) 425 600 ? a+ 2 5 c v dd = 2.0v 435 600 ? a+ 8 5 c pic18lf1220/1320 650 900 ? a -40c 670 900 ? a+ 2 5 c v dd = 3.0v 680 900 ? a+ 8 5 c all devices 1.2 1.8 ma -40c v dd = 5.0v 1.2 1.8 ma +25c 1.2 1.8 ma +85c extended devices 1.2 1.8 ma +125c 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 236 ? 2002-2015 microchip technology inc. supply current (i dd ) (2,3) pic18lf1220/1320 4.7 8 ? a -40c f osc = 31 khz ( rc_idle mode, internal oscillator source) 5.0 8 ? a+ 2 5 c v dd = 2.0v 5.8 11 ? a+ 8 5 c pic18lf1220/1320 7.0 11 ? a -40c 7.8 11 ? a+ 2 5 c v dd = 3.0v 8.7 15 ? a+ 8 5 c all devices 12 16 ? a -40c v dd = 5.0v 14 16 ? a+ 2 5 c 14 22 ? a+ 8 5 c extended devices 25 75 ? a +125c pic18lf1220/1320 75 150 ? a -40c f osc = 1 mhz ( rc_idle mode, internal oscillator source) 85 150 ? a+ 2 5 c v dd = 2.0v 95 150 ? a+ 8 5 c pic18lf1220/1320 110 180 ? a -40c 125 180 ? a+ 2 5 c v dd = 3.0v 135 180 ? a+ 8 5 c all devices 180 380 ? a -40c v dd = 5.0v 195 380 ? a+ 2 5 c 200 380 ? a+ 8 5 c extended devices 350 435 ? a +125c 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 237 pic18f1220/1320 supply current (i dd ) (2,3) pic18lf1220/1320 140 275 ? a -40c f osc = 4 mhz ( rc_idle mode, internal oscillator source) 140 275 ? a+ 2 5 c v dd = 2.0v 150 275 ? a+ 8 5 c pic18lf1220/1320 220 375 ? a -40c 220 375 ? a+ 2 5 c v dd = 3.0v 220 375 ? a+ 8 5 c all devices 390 800 ? a -40c v dd = 5.0v 400 800 ? a+ 2 5 c 380 800 ? a+ 8 5 c extended devices 410 800 ? a +125c pic18lf1220/1320 150 250 ? a -40c f osc = 1 mh z ( pri_run mode, ec oscillator) 150 250 ? a+ 2 5 c v dd = 2.0v 160 250 ? a+ 8 5 c pic18lf1220/1320 340 350 ? a -40c 300 350 ? a+ 2 5 c v dd = 3.0v 280 350 ? a+ 8 5 c all devices 0.72 1.0 ma -40c v dd = 5.0v 0.63 1.0 ma +25c 0.58 1.0 ma +85c extended devices 0.53 1.0 ma +125c 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 238 ? 2002-2015 microchip technology inc. supply current (i dd ) (2,3) pic18lf1220/1320 415 600 ? a -40c f osc = 4 mhz ( pri_run mode, ec oscillator) 425 600 ? a+ 2 5 c v dd = 2.0v 435 600 ? a+ 8 5 c pic18lf1220/1320 0.87 1.0 ma -40c 0.75 1.0 ma +25c v dd = 3.0v 0.75 1.0 ma +85c all devices 1.6 2.0 ma -40c v dd = 5.0v 1.6 2.0 ma +25c 1.5 2.0 ma +85c extended devices 1.5 2.0 ma +125c extended devices 6.3 9.0 ma +125c v dd = 4.2v f osc = 25 mhz ( pri_run mode, ec oscillator) 9.7 10.0 ma +125c v dd = 5.0v all devices 9.4 12 ma -40c f osc = 40 mh z ( pri_run mode, ec oscillator) 9.5 12 ma +25c v dd = 4.2v 9.6 12 ma +85c all devices 11.9 15 ma -40c v dd = 5.0v 12.1 15 ma +25c 12.2 15 ma +85c 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 239 pic18f1220/1320 supply current (i dd ) (2,3) pic18lf1220/1320 35 50 ? a -40c f osc = 1 mhz ( pri_idle mode, ec oscillator) 35 50 ? a+ 2 5 c v dd = 2.0v 35 60 ? a+ 8 5 c pic18lf1220/1320 55 80 ? a -40c 50 80 ? a+ 2 5 c v dd = 3.0v 60 100 ? a+ 8 5 c all devices 105 150 ? a -40c v dd = 5.0v 110 150 ? a+ 2 5 c 115 150 ? a+ 8 5 c extended devices 125 300 ? a +125c pic18lf1220/1320 135 180 ? a -40c f osc = 4 mhz ( pri_idle mode, ec oscillator) 140 180 ? a+ 2 5 c v dd = 2.0v 140 180 ? a+ 8 5 c pic18lf1220/1320 215 280 ? a -40c 225 280 ? a+ 2 5 c v dd = 3.0v 230 280 ? a+ 8 5 c all devices 410 525 ? a -40c v dd = 5.0v 420 525 ? a+ 2 5 c 430 525 ? a+ 8 5 c extended devices 450 800 ? a +125c extended devices 2.2 3.0 ma +125c v dd = 4.2v f osc = 25 mhz ( pri_idle mode, ec oscillator) 2.7 3.5 ma +125c v dd = 5.0v 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 240 ? 2002-2015 microchip technology inc. supply current (i dd ) (2,3) all devices 3.2 4.1 ma -40c f osc = 40 mhz ( pri_idle mode, ec oscillator) 3.2 4.1 ma +25c v dd = 4.2 v 3.3 4.1 ma +85c all devices 4.0 5.1 ma -40c v dd = 5.0v 4.1 5.1 ma +25c 4.1 5.1 ma +85c pic18lf1220/1320 5.1 9 ? a -10c f osc = 32 khz (4) ( sec_run mode, timer1 as clock) 5.8 9 ? a+ 2 5 c v dd = 2.0v 7.9 11 ? a+ 7 0 c pic18lf1220/1320 7.9 12 ? a -10c 8.9 12 ? a+ 2 5 c v dd = 3.0v 10.5 14 ? a+ 7 0 c all devices 12.5 20 ? a -10c v dd = 5.0v 16.3 20 ? a+ 2 5 c 18.4 25 ? a+ 7 0 c 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 241 pic18f1220/1320 supply current (i dd ) (2,3) pic18lf1220/1320 9.2 15 ? a -10c f osc = 32 khz (4) ( sec_idle mode, timer1 as clock) 9.6 15 ? a+ 2 5 c v dd = 2.0v 12.7 18 ? a+ 7 0 c pic18lf1220/1320 22 30 ? a -10c 21 30 ? a+ 2 5 c v dd = 3.0v 20 35 ? a+ 7 0 c all devices 50 80 ? a -10c v dd = 5.0v 45 80 ? a+ 2 5 c 45 80 ? a+ 7 0 c 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 242 ? 2002-2015 microchip technology inc. module differential currents ( ? i wdt , ? i bor , ? i lvd , ? i oscb , ? i ad ) d022 ( ? i wdt ) watchdog timer 1.5 4.0 ? a -40c 2.2 4.0 ? a+ 2 5 c v dd = 2.0v 3.1 5.0 ? a+ 8 5 c 2.5 6.0 ? a -40c 3.3 6.0 ? a+ 2 5 c v dd = 3.0v 4.7 7.0 ? a+ 8 5 c 3.7 10.0 ? a -40c 4.5 10.0 ? a+ 2 5 c v dd = 5.0v 6.1 13.0 ? a+ 8 5 c d022a ( ? i bor ) brown-out reset 19 35.0 ? a-40 ? c to +85 ? cv dd = 3.0v 24 45.0 ? a-40 ? c to +85 ? cv dd = 5.0v d022b ( ? i lvd ) low-voltage detect 8.5 25.0 ? a-40 ? c to +85 ? cv dd = 2.0v 16 35.0 ? a-40 ? c to +85 ? cv dd = 3.0v 20 45.0 ? a-40 ? c to +85 ? cv dd = 5.0v d025 ( ? i oscb ) timer1 oscillator 1.7 3.5 ? a- 4 0 ? c 1.8 3.5 ? a+ 2 5 ? cv dd = 2.0v 32 khz on timer1 (4) 2.1 4.5 ? a+ 8 5 ? c 2.2 4.5 ? a- 4 0 ? c 2.6 4.5 ? a+ 2 5 ? cv dd = 3.0v 32 khz on timer1 (4) 2.8 5.5 ? a+ 8 5 ? c 3.0 6.0 ? a- 4 0 ? c 3.3 6.0 ? a+ 2 5 ? cv dd = 5.0v 32 khz on timer1 (4) 3.6 7.0 ? a+ 8 5 ? c d026 ( ? i ad ) a/d converter 1.0 3.0 ? a-40 ? c to +85 ? cv dd = 2.0v a/d on, not converting 1.0 4.0 ? a-40 ? c to +85 ? cv dd = 3.0v 2.0 10.0 ? a-40 ? c to +85 ? cv dd = 5.0v 1.0 8.0 ? a-40 ? c to +125 ? cv dd = 5.0v 22.2 dc characteristics: power-down and supply current pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ. max. units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the os cillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 243 pic18f1220/1320 22.3 dc characteristics: pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c for industrial -40c ?? t a ? +125c for extended param no. symbol characteristic min. max. units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 4.5v d030a 0.8 v 4.5v ? v dd ?? 5.5v d031 with schmitt trigger buffer v ss 0.2 v dd v d032 mclr v ss 0.2 v dd v d032a osc1 (in xt, hs and lp modes) and t1osi v ss 0.3 v dd v d033 osc1 (in rc and ec mode) (1) v ss 0.2 v dd v v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v ? v dd ?? 5.5v d041 with schmitt trigger buffer 0.8 v dd v dd v d042 mclr , osc1 (ec mode) 0.8 v dd v dd v d042a osc1 (in xt, hs and lp modes) and t1osi 1.6 v dd v dd v d043 osc1 (rc mode) (1) 0.9 v dd v dd v i il input leakage current (2,3) d060 i/o ports ? 1 ? av ss ?? v pin ?? v dd , pin at high-impedance d061 mclr ? 5 ? av ss ?? v pin ?? v dd d063 osc1 ? 5 ? av ss ?? v pin ?? v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 ? av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 244 ? 2002-2015 microchip technology inc. v ol output low voltage d080 i/o ports 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 ? c to +85 ? c d083 osc2/clko (rc mode) 0 . 6 v i ol = 1.6 ma, v dd = 4.5v, -40 ? c to +85 ? c v oh output high voltage (3) d090 i/o ports v dd C 0.7 v i oh = -3.0 ma, v dd = 4.5v, -40 ? c to +85 ? c d092 osc2/clko (rc mode) v dd C 0.7 v i oh = -1.3 ma, v dd = 4.5v, -40 ? c to +85 ? c d150 v od open-drain high voltage 8 . 5 v r a 4 p i n capacitive loading specs on output pins d100 (4) c osc2 osc2 pin 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) 50 pf to meet the ac timing specifications d102 c b scl, sda 400 pf in i 2 c mode 22.3 dc characteristics: pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c for industrial -40c ?? t a ? +125c for extended param no. symbol characteristic min. max. units conditions note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 245 pic18f1220/1320 table 22-1: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. sym. characteristic min. typ? max. units conditions internal program memory programming specifications (1) d110 v pp voltage on mclr /v pp pin 9.00 13.25 v (note 2) d112 i pp current into mclr /v pp pin 5 ? a d113 i ddp supply current during programming 1 0m a data eeprom memory d120 e d byte endurance 100k 1m e/w -40 ? c to +85 ? c d121 v drw v dd for read/write v min 5.5 v using eecon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time 4 ms d123 t retd characteristic retention 40 year provided no other specifications are violated d124 t ref number of total erase/write cycles before refresh (3) 1m 10m e/w -40c to +85c program flash memory d130 e p cell endurance 10k 100k e/w -40 ? c to +85 ? c d131 v pr v dd for read v min 5 . 5vv min = minimum operating voltage d132 v ie v dd for block erase 4.5 5.5 v using icsp port d132a v iw v dd for externally timed erase or write 4.5 5.5 v using icsp port d132b v pew v dd for self-timed write v min 5 . 5vv min = minimum operating voltage d133 t ie icsp? block erase cycle time 4 ms v dd > 4.5v d133a t iw icsp erase or write cycle time (externally timed) 1m s v dd > 4.5v d133a t iw self-timed write cycle time 2 ms d134 t retd characteristic retention 40 year provided no other specifications are violated ? data in typ column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: these specifications are for programming the on-chip program memory through the use of table write instructions. 2: the pin may be kept in this range at times other than programming, but it is not recommended. 3: refer to section 7.8 ?using the data eeprom? for a more detailed discussion on data eeprom endurance. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 246 ? 2002-2015 microchip technology inc. figure 22-4: low-voltage detect characteristics v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software) table 22-2: low-voltage detect characteristics pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ? max. units conditions d420d lvd voltage on v dd transition high-to-low industrial low voltage (-10c to +85c) pic18lf1220/1320 lvdl<3:0> = 0000 n/a n/a n/a v reserved lvdl<3:0> = 0001 n/a n/a n/a v reserved lvdl<3:0> = 0010 2.08 2.26 2.44 v lvdl<3:0> = 0011 2.26 2.45 2.65 v lvdl<3:0> = 0100 2.35 2.55 2.76 v lvdl<3:0> = 0101 2.55 2.77 2.99 v lvdl<3:0> = 0110 2.64 2.87 3.10 v lvdl<3:0> = 0111 2.82 3.07 3.31 v lvdl<3:0> = 1000 3.09 3.36 3.63 v lvdl<3:0> = 1001 3.29 3.57 3.86 v lvdl<3:0> = 1010 3.38 3.67 3.96 v lvdl<3:0> = 1011 3.56 3.87 4.18 v lvdl<3:0> = 1100 3.75 4.07 4.40 v lvdl<3:0> = 1101 3.93 4.28 4.62 v lvdl<3:0> = 1110 4.23 4.60 4.96 v legend: shading of rows is to assist in readability of the table. ? production tested at t amb = 25c. specifications over temperature limits ensured by characterization. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 247 pic18f1220/1320 d420f lvd voltage on v dd transition high-to-low industrial low voltage (-40c to -10c) pic18lf1220/1320 lvdl<3:0> = 0000 n/a n/a n/a v reserved lvdl<3:0> = 0001 n/a n/a n/a v reserved lvdl<3:0> = 0010 1.99 2.26 2.53 v lvdl<3:0> = 0011 2.16 2.45 2.75 v lvdl<3:0> = 0100 2.25 2.55 2.86 v lvdl<3:0> = 0101 2.43 2.77 3.10 v lvdl<3:0> = 0110 2.53 2.87 3.21 v lvdl<3:0> = 0111 2.70 3.07 3.43 v lvdl<3:0> = 1000 2.96 3.36 3.77 v lvdl<3:0> = 1001 3.14 3.57 4.00 v lvdl<3:0> = 1010 3.23 3.67 4.11 v lvdl<3:0> = 1011 3.41 3.87 4.34 v lvdl<3:0> = 1100 3.58 4.07 4.56 v lvdl<3:0> = 1101 3.76 4.28 4.79 v lvdl<3:0> = 1110 4.04 4.60 5.15 v lvd voltage on v dd transition high-to-low industrial (-10c to +85c) d420g pic18f1220/1320 lvdl<3:0> = 1101 3.93 4.28 4.62 v lvdl<3:0> = 1110 4.23 4.60 4.96 v lvd voltage on v dd transition high-to-low industrial (-40c to -10c) d420h pic18f1220/1320 lvdl<3:0> = 1101 3.76 4.28 4.79 v lvdl<3:0> = 1110 4.04 4.60 5.15 v lvd voltage on v dd transition high-to-low extended (-10c to +85c) d420j pic18f1220/1320 lvdl<3:0> = 1101 3.94 4.28 4.62 v lvdl<3:0> = 1110 4.23 4.60 4.96 v lvd voltage on v dd transition high-to-low extended (-40c to -10c, +85c to +125c) d420k pic18f1220/1320 lvdl<3:0> = 1101 3.77 4.28 4.79 v lvdl<3:0> = 1110 4.05 4.60 5.15 v table 22-2: low-voltage detect characteristics (continued) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min. typ? max. units conditions legend: shading of rows is to assist in readability of the table. ? production tested at t amb = 25c. specifications over temperature limits ensured by characterization. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 248 ? 2002-2015 microchip technology inc. 22.4 ac (timing) characteristics 22.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t13cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hh i g h rr i s e i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 249 pic18f1220/1320 22.4.2 timing conditions the temperature and voltages specified in tab l e 2 2- 3 apply to all timing specifications unless otherwise noted. figure 22-5 specifies the load conditions for the timing specifications. table 22-3: temperature and voltage specifications ? ac figure 22-5: load conditions for de vice timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ?? +85c for industrial -40c ?? t a ? +125c for extended operating voltage v dd range as described in dc spec section 22.1 and section 22.3 . lf parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2/clko load condition 1 load condition 2 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 250 ? 2002-2015 microchip technology inc. 22.4.3 timing diagrams and specifications figure 22-6: external clock timing (all modes exce pt pll) table 22-4: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min. max. units conditions 1a f osc external clki frequency (1) dc 40 mhz ec, ecio (lf and industrial) dc 25 mhz ec, ecio (extended) oscillator frequency (1) dc 4 mhz rc oscillator dc 1 mhz xt oscillator dc 25 mhz hs oscillator 1 10 mhz hs + pll oscillator dc 33 khz lp oscillator mode 1t osc external clki period (1) 25 ns ec, ecio (lf and industrial) 40 ns ec, ecio (extended) oscillator period (1) 250 ns rc oscillator 1000 ns xt oscillator 25 100 1000 nsns hs oscillator hs + pll oscillator 30 ? s lp oscillator 2t cy instruction cycle time (1) 100 ns t cy = 4/f osc 3 tosl, to s h external clock in (osc1) high or low time 30 ns xt oscillator 2.5 ? s lp oscillator 10 ns hs oscillator 4t o s r , to s f external clock in (osc1) rise or fall time 20 ns xt oscillator 50 ns lp oscillator 7.5 ns hs oscillator note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumpti on. all devices are tested to operate at min. values with an external clock applied to the osc1/clki pin. when an external clock input is used, the max. cycle time limit is dc (no clock) for all devices. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 251 pic18f1220/1320 table 22-5: pll clock timing specifications, hs/hspll mode (v dd = 4.2v to 5.5v) param no. sym. characteristic min. typ? max. units conditions f10 f osc oscillator frequency range 4 10 mhz hs and hspll mode only f11 f sys on-chip vco system frequency 16 40 mhz hspll mode only f12 t pll pll start-up time (lock time) 2 ms hspll mode only f13 ? clk clko stability (jitter) -2 +2 % hspll mode only ? data in typ column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. table 22-6: internal rc accuracy: pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18f1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device min. typ. max. units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz (1) pic18lf1220/1320 -2 +/-1 2 % +25c v dd = 2.7-3.3v -5 5 % -10c to +85c v dd = 2.7-3.3v -10 10 % -40c to +85c v dd = 2.7-3.3v pic18f1220/ 1320pic18f1220/1320 -2 +/-1 2 % +25c v dd = 4.5-5.5v -5 5 % -10c to +85c v dd = 4.5-5.5v -10 10 % -40c to +85c v dd = 4.5-5.5v intrc accuracy @ freq = 31 khz (2) pic18lf1220/1320 26.562 35.938 khz -40c to +85c v dd = 2.7-3.3v pic18f1220/ 1320pic18f1220/1320 26.562 35.938 khz -40c to +85c v dd = 4.5-5.5v legend: shading of rows is to assist in readability of the table. note 1: frequency calibrated at 25c. osctune register can be used to compensate for temperature and v dd drift. 2: intrc frequency after calibration. 3: change of intrc frequency as v dd changes. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 252 ? 2002-2015 microchip technology inc. figure 22-7: clko and i/o timing table 22-7: clko and i/o timing requirements note: refer to figure 22-5 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param. no. symbol characteristic min. typ. max. units conditions 10 tosh2ckl osc1 ? to clko ? 75 200 ns (note 1) 11 tosh2ckh osc1 ? to clko ? 75 200 ns (note 1) 12 tckr clko rise time 35 100 ns (note 1) 13 tckf clko fall time 35 100 ns (note 1) 14 tckl2iov clko ? to port out valid 0.5 t cy + 20 ns (note 1) 15 tiov2ckh port in valid before clko ? 0.25 t cy + 25 ns (note 1) 16 tckh2ioi port in hold after clko ? 0n s (note 1) 17 tosh2iov osc1 ? (q1 cycle) to port out valid 50 150 ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) pic18f1x20 100 ns 18a pic18lf1x20 200 ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) 0n s 20 tior port output rise time pic18f1x20 10 25 ns 20a pic18lf1x20 60 ns 21 tiof port output fall time pic18f1x20 10 25 ns 21a pic18lf1x20 60 ns note 1: measurements are taken in rc mode, where clko output is 4 x t osc . downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 253 pic18f1220/1320 figure 22-8: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 22-9: brown-out r eset timing v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 22-5 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal internal reference 36 reference voltage voltage stable downloaded from: http:///
pic18f1220/1320 ds30009605g-page 254 ? 2002-2015 microchip technology inc. table 22-8: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset requirements figure 22-10: timer0 and timer1 exte rnal clock timings param. no. symbol characteristic min. typ. max. units conditions 30 tmcl mclr pulse width (low) 2 ? s 31 t wdt watchdog timer time-out period (no postscaler) 3.48 4.00 4.71 ms 32 t ost oscillation start-up timer period 1024 t osc 1024 t osc t osc = osc1 period 33 t pwrt power-up timer period 65.5 132 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset 2 ? s 35 t bor brown-out reset pulse width 200 ? sv dd ? b vdd (see d005) 36 t ivrst time for internal reference voltage to become stable 2 05 0 ? s 37 t lvd low-voltage detect pulse width 200 ? sv dd ? v lvd note: refer to figure 22-5 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t13cki tmr0 or tmr1 downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 255 pic18f1220/1320 table 22-9: timer0 and timer1 external clock requirements figure 22-11: capture/compare/pwm timings (all ccp modules) param no. symbol characteristic min. max. units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 42 tt0p t0cki period no prescaler t cy + 10 ns with prescaler greater of: 20 ns or t cy + 40 n n sn = p r e s c a l e value (1, 2, 4,..., 256) 45 tt1h t13cki high time synchronous, no prescaler 0.5 t cy + 20 ns synchronous, with prescaler pic18f1x20 10 ns pic18lf1x20 25 ns asynchronous pic18f1x20 30 ns pic18lf1x20 50 ns 46 tt1l t13cki low time synchronous, no prescaler 0.5 t cy + 5 ns synchronous, with prescaler pic18f1x20 10 ns pic18lf1x20 25 ns asynchronous pic18f1x20 30 ns pic18lf1x20 50 ns 47 tt1p t13cki input period synchronous greater of: 20 ns or t cy + 40 n n sn = p r e s c a l e value (1, 2, 4, 8) asynchronous 60 ns ft1 t13cki oscillator input frequency range dc 50 khz 48 tcke2tmri delay from external t13cki clock edge to timer increment 2 t osc 7 t osc note: refer to figure 22-5 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 256 ? 2002-2015 microchip technology inc. table 22-10: capture/compare/pwm requirements (all ccp modules) figure 22-12: eusart synchrono us transmission (master/slave) timing table 22-11: eusart synchronous transmission requirements figure 22-13: eusart synchro nous receive (master/slave) timing param. no. symbol characteristic min. max. units conditions 50 tccl ccpx input low time no prescaler 0.5 t cy + 20 ns with prescaler pic18f1x20 10 ns pic18lf1x20 20 ns 51 tcch ccpx input high time no prescaler 0.5 t cy + 20 ns with prescaler pic18f1x20 10 ns pic18lf1x20 20 ns 52 tccp ccpx input period 3 t cy + 40 n ns n = prescale value (1, 4 or 16) 53 tccr ccpx output fall time pic18f1x20 25 ns pic18lf1x20 45 ns 54 tccf ccpx output fall time pic18f1x20 25 ns pic18lf1x20 45 ns param. no. symbol characteristic min. max. units conditions 120 tckh2dtv sync xmit (master & slave) clock high to data out valid pic18f1x20 40 ns pic18lf1x20 100 ns 121 tckrf clock out rise time and fall time (master mode) pic18f1x20 20 ns pic18lf1x20 50 ns 122 tdtrf data out rise time and fall time pic18f1x20 20 ns pic18lf1x20 50 ns 121 121 120 122 rb1/an5/tx/ rb4/an6/rx/ dt/kbi0 pin ck/int1 pin note: refer to figure 22-5 for load conditions. 125 126 note: refer to figure 22-5 for load conditions. rb1/an5/tx/ rb4/an6/rx/ dt/kbi0 pin ck/int1 pin downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 257 pic18f1220/1320 table 22-12: eusart synchronous re ceive requirements table 22-13: a/d converter characteristi cs: pic18f1220/1320 (industrial) pic18lf1220/1320 (industrial) param. no. symbol characteristic min. max. units conditions 125 tdtv2ckl sync rcv (master & slave) data hold before ck ? (dt hold time) 10 ns 126 tckl2dtl data hold after ck ? (dt hold time) 15 ns param no. symbol characteristic min. typ. max. units conditions a01 n r resolution 10 bit ? v ref ? 3.0v a03 e il integral linearity error <1 lsb ? v ref ? 3.0v a04 e dl differential linearity error <1 lsb ? v ref ? 3.0v a06 e off offset error <1 lsb ? v ref ? 3.0v a07 e gn gain error <1 lsb ? v ref ? 3.0v a10 monotonicity guaranteed (2) a20 ? v ref reference voltage range (v refh C v refl ) 3 a v dd C av ss v for 10-bit resolution a21 v refh reference voltage high av ss + 3.0v av dd + 0.3v v for 10-bit resolution a22 v refl reference voltage low av ss C 0.3v av dd C 3.0v v for 10-bit resolution a25 v ain analog input voltage v refl v refh v a28 av dd analog supply voltage v dd C 0.3 v dd + 0.3 v a29 av ss analog supply voltage v ss C 0.3 v ss + 0.3 v a30 z ain recommended impedance of analog voltage source 2 . 5k ? a40 i ad a/d conversion current (v dd ) pic18f1x20 180 ? a average current consumption when a/d is on (note 1) pic18lf1x20 90 ? a a50 i ref v ref input current (note 3) 5 150 ? a ? a during v ain acquisition. during a/d conversion cycle. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current specification includes any such leakage from the a/d module. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: v refh current is from ra3/an3/v ref + pin or av dd , whichever is selected as the v refh source. v refl current is from ra2/an2/v ref - pin or av ss , whichever is selected as the v refl source. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 258 ? 2002-2015 microchip technology inc. figure 22-14: a/d conversion timing table 22-14: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk (1) a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy param no. symbol characteristic min. max. units conditions 130 t ad a/d clock period pic18f1x20 1.6 20 (5) ? st osc based, v ref ? 3.0v pic18lf1x20 3.0 20 (5) ? st osc based, v ref full range pic18f1x20 2.0 6.0 ? s a/d rc mode pic18lf1x20 3.0 9.0 ? s a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 1) 11 12 t ad 132 t acq acquisition time (note 3) 1510 ? s ? s -40 ? c ? te m p ? +125 ? c 0 ? c ? tem p ? +125 ? c 135 t swc switching time from convert ? sample (note 4) 136 t amp amplifier settling time (note 2) 1 ? s this may be used if the new input voltage has not changed by more than 1 lsb (i.e., 5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). note 1: adres register may be read on the following t cy cycle. 2: see section 17.0 ?10-bit analog-to-d igital converter (a/d) module? for minimum conditions when input voltage has changed more than 1 lsb. 3: the time for the holding capacitor to acquire the new input voltage, when the voltage changes full scale after the conversion (av dd to av ss , or av ss to av dd ). the source impedance ( r s ) on the input channels is 50 ? . 4: on the next q4 cycle of the device clock. 5: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 259 pic18f1220/1320 22.5 high temperature operation this section outlines the specifications for the following devices operating in the high temperature range between -40c and 150c. (6) pic18f1220 pic18f1320 when the value of any parameter is identical for both the 125c extended and the 150c high temp. temperature ranges, then that value will be found in the standard specification tables shown earlier in this chapter, under the fields listed for the 125c extended temperature range. if the value of any parameter is unique to the 150c high temp. temperature range, then it will be listed here, in this section of the data sheet. if a silicon errata exists for the product and it lists a modification to the 125c extended temperature range value, one that is also shared at the 150c high temp. temperature range, then that modified value will apply to both temperature ranges. table 22-15: absolute maximum ratings note 1: data contained in this section is applica- ble to the following devices: pic18f1220 and pic18f1320. 2: writes are not allowed for flash program memory above 125c. 3: all ac timing specifications are increased by 30%. 4: figure 22-3 ; the frequency range is decreased to 20 mhz. 5: the temperature range indicator in the catalog part number and device marking is h for -40c to 150c. example: pic18f1220t-h/so indicates the device is shipped in a tape and reel configuration, in the soic package, and is rated for operation from -40c to 150c. 6: aec-q100 reliability testing for devices intended to operate at 150c is 1,000 hours. any design in which the total oper- ating time from 125c to 150c will be greater than 1,000 hours is not warranted without prior written approval from microchip technology inc. parameter source/sink value units max. current: v ss sink 300 ma max. current: v dd source 250 ma max. current: pin sink 20 ma max. current: pin source 15 ma max. port current: all ports combined sink 20 ma max. port current: all ports combined source 15 ma max. junction temperature 155 c note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability. downloaded from: http:///
pic18f1220/1320 ds30009605g-page 260 ? 2002-2015 microchip technology inc. table 22-16: dc characteristics for i dd specifications for pic18f1220/1320-h (high temp.) table 22-17: adc characteristi cs for pic18f1220/1320-h (high temp.) symbol device characteristics min. typ. max. units condition v dd note i pd power down current 220 ? a 5.0 sleep mode i dd supply current 250 ? a5 . 0f osc = 31 khz (rc_run mode, internal oscillator source) i dd supply current 800 ? a5 . 0f osc = 1 mhz (rc_run mode, internal oscillator source) i dd supply current 2.0 ma 5.0 f osc = 4 mhz (rc_run mode, internal oscillator source) i dd supply current 240 ? a5 . 0f osc = 31 khz (rc_idle mode, internal oscillator source) i dd supply current 600 ? a5 . 0f osc = 1 mhz (rc_idle mode, internal oscillator source) i dd supply current 1.0 ma 5.0 f osc = 4 mhz (rc_idle mode, internal oscillator source) i dd supply current 1.2 ma 5.0 f osc = 1 mhz (pri_run mode, ec oscillator) i dd supply current 2.2 ma 5.0 f osc = 4 mhz (pri_run mode, ec oscillator) i dd supply current 10.0 ma 5.0 f osc = 20 mhz (pri_run mode, ec oscillator) i dd supply current 500 ? a5 . 0f osc = 1 mhz (pri_idle mode, ec oscillator) i dd supply current 1.0 ma 5.0 f osc = 4 mhz (pri_idle mode, ec oscillator) i dd supply current 3.5 ma 5.0 f osc = 20 mhz (pri_idle mode, ec oscillator) param no. sym. characteristic min. typ. max. units conditions d026 a/d conv 3 0 ? av dd = 5.0v, a/d on, not converting downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 261 pic18f1220/1320 table 22-18: dc characteristics for i pd specifications for pic18f1220/1320-h (high temp.) table 22-19: external cl ock timing requirements for pic18f1220/1320-h (high temp.) table 22-20: internal rc accuracy for pic18f1220/1320-h (high temp.) param no. sym. device characteristics min. typ. max. units d030 v il i/o ports with ttl buffer supply current v ss 0 . 2 0 v dd ? av dd < 4.5v d030a v il v ss 0.7 v 4.5v ?? v dd ?? 5.5v d031 v il i/o ports with schmitt trigger buffer v ss 0 . 2 5 v dd v d032 v il mclr v ss 0 . 2 5 v dd v d032a v il osc1 (xt, hs and lp modes) and t1osi v ss 0 . 3 5 v dd v d033 v il osc1 (rc and ec modes) v ss 0 . 2 5 v dd v d040 v ih i/o with ttl buffer 0.3 v dd + 0.8v v dd vv dd < 4.5v d040a v ih 2.1 v dd v4.5v ?? v dd ?? 5.5v d041 v ih i/o ports with schmitt trigger buffer 0.85 v dd v dd v d042 v ih mclr , osc1 (ec mode) 0.85 v dd v dd v d042a v ih osc1 (xt, hs and lp modes) and t1osi 1.65 v dd v d070 i purb port b weak pull-up current 25 450 ? av dd = 5v, v pin = v ss i ab combined source current for ports a and b 1 5 m a v dd = 4.5v, i oh = 3.0 ma, v pin = v oh i ab combined sink current for ports a and b 2 5 m a v dd = 4.5v, i ol = 8.5 ma, v pin = v ol param no. sym. characteristic min. typ. max. units conditions 1a f osc external clki frequency dc 20 mhz ec, ecio (extended) 1a f osc oscillator frequency dc 20 mhz hs oscillator 1t osc external clki period 50 ns ec, ecio (extended) 1t osc oscillator period 50 ns hs oscillator param no. device min. typ. max. units temp. conditions pic18f1220/1320 2.0 2.0 % 25c 4.5v ?? v dd ?? 5.5v pic18f1220/1320 20 20 % -40c to ? 150c 4.5v ?? v dd ?? 5.5v downloaded from: http:///
pic18f1220/1320 ds30009605g-page 262 ? 2002-2015 microchip technology inc. 23.0 dc and ac characteristics graphs and tables typical represents the mean of the distribution at 25 ? c. maximum or minimum represents (mean + 3 ? ) or (mean C 3 ? ) respectively, where ? is a standard deviation, over the whole temperature range. figure 23-1: typical i dd vs. f osc over v dd pri_run, ec mode, +25c figure 23-2: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +85c note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0.0 0.1 0.2 0.3 0.4 0.5 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 263 pic18f1220/1320 figure 23-3: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +125c figure 23-4: typical i dd vs. f osc over v dd pri_run, ec mode, +25c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 264 ? 2002-2015 microchip technology inc. figure 23-5: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +125c figure 23-6: typical i dd vs. f osc over v dd pri_run, ec mode, +25c 0.0 0.5 1.0 1.5 2.0 2.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 265 pic18f1220/1320 figure 23-7: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +125c figure 23-8: typical i dd vs. f osc over v dd pri_idle, ec mode, +25c 0 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 266 ? 2002-2015 microchip technology inc. figure 23-9: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +85c figure 23-10: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +125c 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.090 0.100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 267 pic18f1220/1320 figure 23-11: typical i dd vs. f osc over v dd pri_idle, ec mode, +25c figure 23-12: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +125c yp _ 0 100 200 300 400 500 600 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd ( ? a) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0 100 200 300 400 500 600 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd ( ? a) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 268 ? 2002-2015 microchip technology inc. figure 23-13: typical i dd vs. f osc over v dd pri_idle, ec mode, +25c figure 23-14: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 269 pic18f1220/1320 figure 23-15: typical i pd vs. v dd (+25c), 125 khz to 8 mhz rc_run mode, all peripherals disabled figure 23-16: maximum i pd vs. v dd (-40c to +125c), 125 khz to 8 mhz rc_run mode, all peripherals disabled 0 500 1000 1500 2000 2500 3000 2 . 02 . 53 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v) i pd ( ? a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0 500 1000 1500 2000 2500 3000 3500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 270 ? 2002-2015 microchip technology inc. figure 23-17: typical and maximum i pd vs. v dd (-40c to +125c), 31.25 khz rc_run mode, all peripherals disabled figure 23-18: typical i pd vs. v dd (+25c), 125 khz to 8 mhz rc_idle mode, all peripherals disabled 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typ (+25c) max (+85c) max (+125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 271 pic18f1220/1320 figure 23-19: maximum i pd vs. v dd (-40c to +125c), 125 khz to 8 mhz rc_idle mode, all peripherals disabled figure 23-20: typical and maximum i pd vs. v dd (-40c to +125c), 31.25 khz rc_idle mode, all peripherals disabled 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typ (+25c) max (+85c) max (+125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 272 ? 2002-2015 microchip technology inc. figure 23-21: i pd sec_run mode, -10c to +70c, 32.768 khz xtal, 2 x 22 pf, all peripherals disabled figure 23-22: i pd sec_idle mode, -10c to +70c, 32.768 khz, 2 x 22 pf, all peripherals disabled 0 10 20 30 40 50 60 70 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typ (+25c) max (+70c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0 2 4 6 8 10 12 14 16 18 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typ (+25c) max (+70c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 273 pic18f1220/1320 figure 23-23: total i pd , -40c to +125c sleep mode, all peripherals disabled figure 23-24: v oh vs. i oh over temperature (-40c to +125c), v dd = 3.0v 0.001 0.01 0.1 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) max (+85c) max (+125c) typ (+25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i oh (-ma) v oh (v) max (+125c) min (+125c) typ (+25c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 274 ? 2002-2015 microchip technology inc. figure 23-25: v oh vs. i oh over temperature (-40c to +125c), v dd = 5.0v figure 23-26: v ol vs. i ol over temperature (-40c to +125c), v dd = 3.0v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5 10 15 20 25 i oh (-ma) v oh (v) max (+125c) min (+125c) typ (+25c) p( ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (+125c) max (+85c) typ (+25c) min (+125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 275 pic18f1220/1320 figure 23-27: v ol vs. i ol over temperature (-40c to +125c), v dd = 5.0v figure 23-28: ? i pd timer1 oscillator, -10c to +70c sleep mode, tmr1 counter disabled 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (+125c) max (+85c) typ (+25c) min (+125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 . 02 . 53 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v) i pd ( ? a) typ (+25c) max (-10c to +70c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 276 ? 2002-2015 microchip technology inc. figure 23-29: ? i pd fscm vs. v dd over temperature pri_idle mode, ec oscillator at 32 khz, -40c to +125c figure 23-30: ? i pd wdt, -40c to +125c sleep mode, all peripherals disabled 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i pd ( ? a) typ (+25c) max (-40c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0 2 4 6 8 10 12 14 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i pd ( ? a) typ (+25c) max (+85c) max (+125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 277 pic18f1220/1320 figure 23-31: ? i pd lvd vs. v dd sleep mode, lvdl3:lvdl0 = 0001 (2v) figure 23-32: ? i pd bor vs. v dd , -40c to +125c sleep mode, borv1:borv0 = 11 (2v) 0 5 10 15 20 25 30 35 40 45 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typ (+25c) max (+85c) max (+125c) low-voltage detection range normal operating range typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0 5 10 15 20 25 30 35 40 2 . 02 . 53 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v) i pd ( ? a) max (+125c) typ (+25c) device may be in reset device is operating typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) downloaded from: http:///
pic18f1220/1320 ds30009605g-page 278 ? 2002-2015 microchip technology inc. figure 23-33: ? i pd a/d, -40c to +125c sleep mode, a/d enabled (not converting) figure 23-34: average f osc vs. v dd for various r?s external rc mode, c = 20 pf, temperature = +25c 0.001 0.01 0.1 1 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) max (+125c) max (+85c) typ (+25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to +125c) minimum: mean C 3 ? (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 5.1k 10k 33k 100k operation above 4 mhz is not recomended downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 279 pic18f1220/1320 figure 23-35: average f osc vs. v dd for various r?s external rc mode, c = 100 pf, temperature = +25c figure 23-36: average f osc vs. v dd for various r?s external rc mode, c = 300 pf, temperature = +25c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 5.1k 10k 33k 100k 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 5.1k 10k 33k 100k downloaded from: http:///
pic18f1220/1320 ds30009605g-page 280 ? 2002-2015 microchip technology inc. 24.0 packaging information 24.1 package marking information 18-lead pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic18f1320-i/p 0710017 18-lead soic xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f1220- e/so 0710017 20-lead ssop xxxxxxxxxxx xxxxxxxxxxx yywwnnn example pic18f1220- e/ss 0710017 28-lead qfn xxxxxxxx xxxxxxxx yywwnnn example 18f1320 -i/ml 0710017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e 3 e 3 e downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 281 pic18f1220/1320 24.2 package details the following sections give the technical details of the packages. 18-lead plastic dual in-line (p) ? 300 mil body [pdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 18 pitch e .100 bsc top to seating plane a ? ? .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .300 .310 .325 molded package width e1 .240 .250 .280 overall length d .880 .900 .920 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .014 upper lead width b1 .045 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n e1 d 1 2 3 a a1 a2 l ee b c e b1 b microchip technology drawing c04-007b downloaded from: http:///
pic18f1220/1320 ds30009605g-page 282 ? 2002-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 283 pic18f1220/1320 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
pic18f1220/1320 ds30009605g-page 284 ? 2002-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 285 pic18f1220/1320 20-lead plastic shrink small outline (ss) ? 5.30 mm body [ssop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.20 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 20 pitch e 0.65 bsc overall height a C C 2.00 molded package thickness a2 1.65 1.75 1.85 standoff a1 0.05 C C overall width e 7.40 7.80 8.20 molded package width e1 5.00 5.30 5.60 overall length d 6.90 7.20 7.50 foot length l 0.55 0.75 0.95 footprint l1 1.25 ref lead thickness c 0.09 C 0.25 foot angle 0 4 8 lead width b 0.22 C 0.38 l l1 a2 c b a1 a 12 note 1 e1 e d n microchip technology drawing c04-072b downloaded from: http:///
pic18f1220/1320 ds30009605g-page 286 ? 2002-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 287 pic18f1220/1320 downloaded from: http:///
pic18f1220/1320 ds30009605g-page 288 ? 2002-2015 microchip technology inc. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 289 pic18f1220/1320

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pic18f1220/1320 ds30009605g-page 290 ? 2002-2015 microchip technology inc. appendix a: revision history revision a (august 2002) original data sheet for pic18f1220/1320 devices. revision b (november 2002) this revision includes significant changes to section 2.0 , section 3.0 and section 19.0 , as well as updates to the electrical specifications in section 22.0 and includes minor corrections to the data sheet text. revision c (may 2004) this revision includes updates to the electrical specifi- cations in section 22.0 , the dc and ac characteristics graphs and tables in section 23.0 and includes minor corrections to the data sheet text. revision d (october 2006) this revision includes updates to the packaging diagrams. revision e (january 2007) this revision includes updates to the packaging diagrams. revision f (february 2007) this revision includes updates to the packaging diagrams. revision g (april 2015) added section 22.5: high temperature operation in the electrical specifications section. appendix b: device differences the differences between the devices listed in this data sheet are shown in tab l e b - 1 . table b-1: device differences features pic18f1220 pic18f1320 program memory (bytes) 4096 8192 program memory (instructions) 2048 4096 interrupt sources 15 15 i/o ports ports a, b ports a, b enhanced capture/compare/pwm modules 1 1 10-bit analog-to-digital module 7 input channels 7 input channels packages 18-pin sdip 18-pin soic 20-pin ssop 28-pin qfn 18-pin sdip 18-pin soic 20-pin ssop 28-pin qfn downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 291 pic18f1220/1320 appendix c: conversion considerations this appendix discusses the considerations for con- verting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available downloaded from: http:///
pic18f1220/1320 ds30009605g-page 292 ? 2002-2015 microchip technology inc. appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442? . the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and differences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration? . this application note is available as literature number ds00726. downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 293 pic18f1220/1320 the microchip web site microchip provides online support via our web site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: product support C data sheets and errata, appli- cation notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on cus- tomer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://www.microchip.com/support downloaded from: http:///
pic18f1220/1320 ds30009605g-page 294 ? 2002-2015 microchip technology inc. pic18f1220/1320 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. part no. ? x /xx xxx pattern package temperature range device device: pic18f1220/1320 (1) , pic18f1220/1320t (2) ; v dd range 4.2v to 5.5v pic18lf1220/1320 (1) , pic18lf1220/1320t (2) ; v dd range 2.5v to 5.5v temperature range: i=-40 ? c to +85 ? c (industrial) e=-40 ? c to +125 ? c (extended) package: so = soic ss = ssop p=pdip ml=qfn pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf1320-i/p 301 = industrial temp., pdip package, extended v dd limits, qtp pattern #301. b) pic18lf1220-i/so = industrial temp., soic package, extended v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel C soic package only downloaded from: http:///
? 2002-2015 microchip technology inc. ds30009605g-page 295 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2002-2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-236-7 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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